FPGA万年历程序

alarmclock(clk_200Hz,EN,SW1,SW2,hour1,hour0,minute1,minute0,second1,second0,alarm,alar mclock_disp_select);

output alarm;//闹钟时间到的提示信号输出

output[5:0]alarmclock_disp_select;//闹钟设置中位选信号

input EN;//闹钟的设置使能

input SW1,SW2;

input clk_200Hz;//设置中的闪烁显示的时钟

input[3:0]hour1,hour0,minute1,minute0,second1,second0;//当前时间

reg[5:0]alarmclock_disp_select;

reg alarm;

reg[3:0]hour_set1,hour_set0;//存放设置的小时

reg[3:0]minute_set1,minute_set0;//存放设置的分

reg[3:0]second_set1,second_set0;//存放设置的秒

reg[2:0]disp_drive;//设置闹钟时间时，数码管显示的动态位选择（即显示当前位置）

/*闹钟一直工作（与当前时间比较）*/

always

begin

if((hour_set1==hour1)&&(hour_set0==hour0)&&(minute_set1==minute1)&&(minute_set0==mi nute0)&&(second_set1==second1)&&(second_set0==second0))alarm<=1'b1;

else

alarm<=1'b0;

end

/*闹钟设置中，按SW1一次，将移位一次，闪烁显示当前设置位数字*/

always@(posedge SW1)

begin

if(EN==1'b1)

begin

if(disp_drive!=3'b101)

disp_drive<=disp_drive+3'b1;

else

disp_drive<=3'b000;

end

end

/*当前位的闹钟数字设置，按SW2一次，数字增加1*/

always@(posedge SW2)

begin

case(disp_drive)

3'b000:begin

if(hour_set1<4'b0010)

hour_set1<=hour_set1+4'b1;

else

hour_set1<=4'b0;

end

3'b001:begin

if((hour_set1<4'b0010)&&(hour_set0<4'b1001))

hour_set0<=hour_set0+4'b1;

else if((hour_set1==4'b0010)&&(hour_set0<4'b0100))

hour_set0<=hour_set0+4'b1;

else

hour_set0<=4'b0;

end

3'b010:begin

if(minute_set1<4'b0101)

minute_set1<=minute_set1+4'b1;

else

minute_set1<=4'b0;

end

3'b011:begin

if(minute_set0<4'b1001)minute_set0<=minute_set0+4'b1;

else

minute_set0<=4'b0;

end

3'b100:begin

if(second_set1<4'b0101)

second_set1<=second_set1+4'b1;

else

second_set1<=4'b0;

end

3'b101:begin

if(second_set0<4'b1001)

second_set0<=second_set0+4'b1;

else

second_set0<=4'b0;

end

default:begin

end

endcase

end

/*闪烁显示*/

always@(posedge clk_200Hz)

begin

case(disp_drive)

3'b000:alarmclock_disp_select<=6'b100000;

3'b001:alarmclock_disp_select<=6'b010000;

3'b010:alarmclock_disp_select<=6'b001000;

3'b011:alarmclock_disp_select<=6'b000100;

3'b100:alarmclock_disp_select<=6'b000010;

3'b101:alarmclock_disp_select<=6'b000001;

default:alarmclock_disp_select<=6'b000000;

endcase

end

Endmodule

module

disp_data_mux(Timepiece_EN,TimeSet_EN,Stopwatch_EN,time_disp_select,Alarmclock_EN,ala rmclock_disp_select,hour1,hour0,minute1,minute0,second1,second0,Date_EN,DateSet_EN,date_ disp_select,year3,year2,year1,year0,month1,month0,day1,day0,disp_select,disp_data);

output[7:0]disp_select;

output[6:0]disp_data;input Timepiece_EN;

input TimeSet_EN;

input Stopwatch_EN;

input[5:0]time_disp_select;

input Alarmclock_EN;

input[5:0]alarmclock_disp_select;

input[3:0]hour1,hour0,minute1,minute0,second1,second0;

input Date_EN;

input DateSet_EN;

input[7:0]date_disp_select;

input[3:0]year3,year2,year1,year0,month1,month0,day1,day0;

reg[5:0]disp_select;

reg[6:0]disp_data;

reg[3:0]Data;

always@(Timepiece_EN,TimeSet_EN,Stopwatch_EN,time_disp_select,Alarmclock_EN,alarmclo ck_disp_select,hour1,hour0,minute1,minute0,second1,second0,Date_EN,DateSet_EN,date_disp_s elect,month1,month0,day1,day0,disp_select)

begin

/*时钟、秒表显示*/

if((Timepiece_EN||TimeSet_EN||Stopwatch_EN)==1'b1)

begin

disp_select<=time_disp_select;

case(time_disp_select)

6'b100000:Data<=hour1;

6'b010000:Data<=hour0;

6'b001000:Data<=minute1;

6'b000100:Data<=minute0;

6'b000010:Data<=second1;

6'b000001:Data<=second0;

default:Data<=4'b0;

endcase

end

/*闹钟设置显示*/

else if(Alarmclock_EN==1'b1)

begin

disp_select<=alarmclock_disp_select;

case(alarmclock_disp_select)

6'b100000:Data<=hour1;

6'b010000:Data<=hour0;

6'b001000:Data<=minute1;6'b000100:Data<=minute0;

6'b000010:Data<=second1;

6'b000001:Data<=second0;

default:Data<=4'b0;

endcase

end

/*日期以及日期设置显示*/

else if((Date_EN||DateSet_EN)==1'b1)

begin

disp_select<=date_disp_select;

case(date_disp_select)

8'b10000000:Data<=year3;

8'b01000000:Data<=year2;

8'b00100000:Data<=year1;

8'b00010000:Data<=year0;

8'b00001000:Data<=month1;

8'b00000100:Data<=month0;

8'b00000010:Data<=day1;

8'b00000001:Data<=day0;

default:Data<=4'b0;

endcase

end

/*显示数据译码*/

case(Data)

4'b0000:disp_data<=8'hc0;

4'b0001:disp_data<=8'hf9;

4'b0010:disp_data<=8'ha4;

4'b0011:disp_data<=8'hb0;

4'b0100:disp_data<=8'h99;

4'b0101:disp_data<=8'h92;

4'b0110:disp_data<=8'h82;

4'b0111:disp_data<=8'hf8;

4'b1000:disp_data<=8'h80;

4'b1001:disp_data<=8'h90;

default:disp_data<=8'h0;

endcase

end

endmodule

module

date_disp_select(clk_1kHz,clk_200Hz,Date_EN,DateSet_EN,DateSet_disp_drive,Date_disp_sele ct);

output[7:0]Date_disp_select;

input clk_1kHz;

input clk_200Hz;

input Date_EN;

input DateSet_EN;

input[3:0]DateSet_disp_drive;

reg[7:0]Date_disp_select;

reg[3:0]auto_disp_drive;

reg clk;

reg[3:0]disp_drive;

always@(posedge clk_1kHz)/*实现自动运行模式中的动态显示“位选的驱动”*/ begin

if(auto_disp_drive<4'b0111)

auto_disp_drive<=auto_disp_drive+4'b1;

else

auto_disp_drive<=4'b0;

end

always@(Date_EN or DateSet_EN)/*实现自动运行模式中时间动态显示位选驱动与时间设置中的时间动态显示位选驱动的二选一*/

begin

if(Date_EN==1'b1)

begin

clk<=clk_1kHz;

disp_drive<=auto_disp_drive;

end

else if(DateSet_EN==1'b1)

begin

clk<=clk_200Hz;

disp_drive<=DateSet_disp_drive;

end

end

always@(posedge clk)/*实现时间的动态位选*/begin

case(disp_drive)

4'b0000:Date_disp_select<=8'b10000000;

4'b0001:Date_disp_select<=8'b01000000;

4'b0010:Date_disp_select<=8'b00100000;

4'b0011:Date_disp_select<=8'b00010000;

4'b0100:Date_disp_select<=8'b00001000;

4'b0101:Date_disp_select<=8'b00000100;

4'b0110:Date_disp_select<=8'b00000010;

4'b0111:Date_disp_select<=8'b00000001;

default:Date_disp_select<=8'b00000000;

endcase

end

endmodule

module stopwatch(clk1,clk2,EN,F_out);

output F_out;

input EN;

input clk1,clk2;

reg F_out;

always@(EN,clk1,clk2)

begin

case(EN)

1'b0:F_out<=clk1;

1'b1:F_out<=clk2;

default:F_out<=1'b0;

endcase

end

Endmodule

module

time_disp_select(clk_1kHz,clk_200Hz,Time_EN,TimeSet_EN,timeset_disp_drive,time_disp_sele ct);

output[5:0]time_disp_select;

input clk_1kHz;

input clk_200Hz;

input Time_EN;

input TimeSet_EN;

input[2:0]timeset_disp_drive;

reg[5:0]time_disp_select;

reg[2:0]auto_disp_drive;reg clk;

reg[2:0]disp_drive;

always@(posedge clk_1kHz)/*实现自动运行模式中的动态显示“位选的驱动”*/ begin

if(auto_disp_drive<3'b101)

auto_disp_drive<=auto_disp_drive+3'b1;

else

auto_disp_drive<=3'b0;

end

always/*实现自动运行模式中时间动态显示位选驱动与时间设置中的时间动态显示位选驱动的二选一*/

begin

if(Time_EN==1'b1)

begin

clk<=clk_1kHz;

disp_drive<=auto_disp_drive;

end

else if(TimeSet_EN==1'b1)

begin

clk<=clk_200Hz;

disp_drive<=timeset_disp_drive;

end

end

always@(posedge clk)/*实现时间的动态位选*/

begin

case(disp_drive)

3'b000:time_disp_select<=6'b100000;

3'b001:time_disp_select<=6'b010000;

3'b010:time_disp_select<=6'b001000;

3'b011:time_disp_select<=6'b000100;

3'b100:time_disp_select<=6'b000010;

3'b101:time_disp_select<=6'b000001;

default:time_disp_select<=6'b000000;

endcase

end

endmodule

module

Date_mux(year_3,year_2,year_1,year_0,month_1,month_0,date_1,date_0,DateSet_EN,year_data3, year_data2,year_data1,year_data0,month_data1,month_data0,date_data1,date_data0,yeardata_set3,yeardata_set2,yeardata_set1,yeardata_set0,monthdata_set1,monthdata_set0,datedata_set1,datedata _set0);

output[3:0]year_3;

output[3:0]year_2;

output[3:0]year_1;

output[3:0]year_0;

output[3:0]month_1;

output[3:0]month_0;

output[3:0]date_1;

output[3:0]date_0;

input DateSet_EN;//时间设置使能信号

input[3:0]year_data3;//自动模式中当前时间的小时输入

input[3:0]year_data2;//自动模式中当前时间的分钟输入

input[3:0]year_data1;//自动模式中当前时间的秒输入

input[3:0]year_data0;//时间设置后的小时输入

input[3:0]month_data1;//时间设置后的分钟输入

input[3:0]month_data0;

input[3:0]date_data1;

input[3:0]date_data0;

input[3:0]yeardata_set3;

input[3:0]yeardata_set2;

input[3:0]yeardata_set1;

input[3:0]yeardata_set0;

input[3:0]monthdata_set1;

input[3:0]monthdata_set0;

input[3:0]datedata_set1;

input[3:0]datedata_set0;

reg[3:0]year_3;

reg[3:0]year_2;

reg[3:0]year_1;

reg[3:0]year_0;

reg[3:0]month_1;

reg[3:0]month_0;

reg[3:0]date_1;

reg[3:0]date_0;

always@(year_3,year_2,year_1,year_0,month_1,month_0,date_1,date_0,DateSet_EN,year_data3, year_data2,year_data1,year_data0,month_data1,month_data0,date_data1,date_data0,yeardata_set3, yeardata_set2,yeardata_set1,yeardata_set0,monthdata_set1,monthdata_set0,datedata_set1,datedata _set0)

begin

if(DateSet_EN==1'b1)

begin

year_3<=yeardata_set3;

year_2<=yeardata_set2;year_1<=yeardata_set1;

year_0<=yeardata_set0;

month_1<=monthdata_set1;

month_0<=monthdata_set0;

date_1<=datedata_set1;

date_0<=datedata_set0;

end

else

begin

year_3<=year_data3;

year_2<=year_data2;

year_1<=year_data1;

year_0<=year_data0;

month_1<=month_data1;

month_0<=month_data0;

date_1<=date_data1;

date_0<=date_data0;

end

end

Endmodule

module

time_mux(TimeSet_EN,hour1,hour0,minute1,minute0,second1,second0,hour_set1,hour_set0,minu te_set1,minute_set0,second_set1,second_set0,hour_1,hour_0,minute_1,minute_0,second_1,second _0);

output[3:0]hour_1,hour_0;//当前需要显示的小时输出

output[3:0]minute_1,minute_0;//当前需要显示的分钟输出

output[3:0]second_1,second_0;//当前需要显示的秒输出

input TimeSet_EN;//时间设置使能信号

input[3:0]hour1,hour0;//自动模式中当前时间的小时输入

input[3:0]minute1,minute0;//自动模式中当前时间的分钟输入

input[3:0]second1,second0;//自动模式中当前时间的秒输入

input[3:0]hour_set1,hour_set0;//时间设置后的小时输入

input[3:0]minute_set1,minute_set0;//时间设置后的分钟输入

input[3:0]second_set1,second_set0;//时间设置后的秒输入

reg[3:0]hour_1,hour_0;

reg[3:0]minute_1,minute_0;

reg[3:0]second_1,second_0;

/*时间自动显示与时间调整与设置中显示数据的多路选择*/

always@(TimeSet_EN,hour1,hour0,minute1,minute0,second1,second0,hour_set1,hour_set0,minut e_set1,minute_set0,second_set1,second_set0)begin

if(TimeSet_EN==1'b1)

begin

hour_1<=hour_set1;

hour_0<=hour_set0;

minute_1<=minute_set1;

minute_0<=minute_set0;

second_1<=second_set1;

second_0<=second_set0;

end

else

begin

hour_1<=hour1;

hour_0<=hour0;

minute_1<=minute1;

minute_0<=minute0;

second_1<=second1;

second_0<=second0;

end

end

Endmodule

module

anjiandate(DateSet_EN,sw1,sw2,year_data3,year_data2,year_data1,year_data0,month_data1,mont h_data0,date_data1,date_data0,yeardata_set3,yeardata_set2,yeardata_set1,yeardata_set0,monthdat a_set1,monthdata_set0,datedata_set1,datedata_set0,Disp_drive);

input DateSet_EN;

input sw1;

input sw2;

input[3:0]year_data3;

input[3:0]year_data2;

input[3:0]year_data1;

input[3:0]year_data0;

input[3:0]month_data1;

input[3:0]month_data0;

input[3:0]date_data1;

input[3:0]date_data0;

output[3:0]yeardata_set3;

output[3:0]yeardata_set2;

output[3:0]yeardata_set1;

output[3:0]yeardata_set0;

output[3:0]monthdata_set1;

output[3:0]monthdata_set0;

output[3:0]datedata_set1;

output[3:0]datedata_set0;

output[3:0]Disp_drive;

reg[3:0]yeardata_set3;

reg[3:0]yeardata_set2;

reg[3:0]yeardata_set1;

reg[3:0]yeardata_set0;

reg[3:0]monthdata_set1;

reg[3:0]monthdata_set0;

reg[3:0]datedata_set1;

reg[3:0]datedata_set0;

reg[3:0]Disp_drive;

initial

begin

yeardata_set3<=year_data3;

yeardata_set2<=year_data2;

yeardata_set1<=year_data1;

yeardata_set0<=year_data0;

monthdata_set1<=month_data1;

monthdata_set0<=month_data0;

datedata_set1<=date_data1;

datedata_set0<=date_data0;

end

always@(posedge sw1)

begin

if(DateSet_EN==1)

begin

if(Disp_drive<4'b0111)

Disp_drive<=Disp_drive+3'b1;

else

Disp_drive<=3'b0;

end

end

always@(posedge sw2)

begin

if(DateSet_EN==1)

begincase(Disp_drive)

4'b0000:

begin

if(yeardata_set3<4'b1001)

yeardata_set3<=yeardata_set3+4'b1;

else

yeardata_set3<=4'b0;

end

4'b0001:

begin

if(yeardata_set2<4'b1001)

yeardata_set2<=yeardata_set2+4'b1;

else

yeardata_set2<=0;

end

4'b0010:

begin

if(yeardata_set1<4'b1001)

yeardata_set1<=yeardata_set1+4'b1;

else

yeardata_set1<=4'b0;

end

4'b0011:

begin

if(yeardata_set0<4'b1001)

yeardata_set0<=yeardata_set0+4'b1;

else

yeardata_set0<=4'b0;

end

4'b0100:

begin

if(monthdata_set1<4'b0001)

monthdata_set1<=monthdata_set1+4'b1;

else

monthdata_set1<=4'b0;

end

4'b0101:

begin

if((monthdata_set1<4'b0001)&&(monthdata_set0<4'b1001))

monthdata_set0<=monthdata_set0+4'b1;

else if((monthdata_set1==4'b0001)&&(monthdata_set0<4'b0010)) monthdata_set0<=monthdata_set0+4'b1;

else

monthdata_set0<=4'b0;end

4'b0110:

begin

if(datedata_set1<4'b1001)

datedata_set1<=datedata_set1+4'b1;

else

datedata_set1<=4'b0;

end

4'b0111:

begin

if(datedata_set0<4'b1001)

datedata_set0<=datedata_set0+4'b1;

else

datedata_set0<=4'b0;

end

endcase

end

end

endmodule

module

anjian(TimeSet_EN,sw1,sw2,hour1,hour0,minute1,minute0,second0,second1,hour_set1,hour_set0, minute_set1,minute_set0,second_set1,second_set0,disp_drive);

input TimeSet_EN;

input sw1;

input sw2;

input[3:0]hour1;

input[3:0]hour0;

input[3:0]minute1;

input[3:0]minute0;

input[3:0]second1;

input[3:0]second0;

output[3:0]hour_set1;

output[3:0]hour_set0;

output[3:0]minute_set1;

output[3:0]minute_set0;

output[3:0]second_set1;

output[3:0]second_set0;

output[2:0]disp_drive;

reg[3:0]hour_set1;reg[3:0]hour_set0;

reg[3:0]minute_set1;

reg[3:0]minute_set0;

reg[3:0]second_set1;

reg[3:0]second_set0;

reg[2:0]disp_drive;

initial

begin

hour_set1<=hour1;

hour_set0<=hour0;

minute_set1<=minute1;

minute_set0<=minute0;

second_set1<=second1;

second_set0<=second0;

end

always@(posedge sw1)

begin

if(TimeSet_EN==1)

begin

if(disp_drive<3'b101)

disp_drive<=disp_drive+3'b1;

else

disp_drive<=3'b0;

end

end

always@(posedge sw2)

begin

if(TimeSet_EN==1)

begin

case(disp_drive)

3'b000:

begin

if(hour_set1<4'b0010)

hour_set1<=hour_set1+4'b1;

else

hour_set1<=4'b0;

end

3'b001:

begin

if((hour_set1<4'b0010)&&(hour_set0<4'b1001))hour_set0<=hour_set0+4'b1;

else if((hour_set1==4'b0010)&&(hour_set0<4'b0100))

hour_set0<=hour_set0+4'b1;

else

hour_set0<=4'b0;

end

3'b010:

begin

if(minute_set1<4'b0101)

minute_set1<=minute_set1+4'b1;

else

minute_set1<=4'b0;

end

3'b011:

begin

if(minute_set0<4'b1001)

minute_set0<=minute_set0+4'b1;

else

minute_set0<=4'b0;

end

3'b100:

begin

if(second_set1<4'b0101)

second_set1<=second_set1+4'b1;

else

second_set1<=4'b0;

end

3'b101:

begin

if(second_set0<4'b1001)

second_set0<=second_set0+4'b1;

else

second_set0<=4'b0;

end

endcase

end

end

endmodule

module

maincontrol(SW3,Timepiece_EN,TimeSet_EN,Stopwatch_EN,Alarmclock_EN,Date_EN,DateSet _EN,led);output[7:0]led;

output Timepiece_EN;//时间自动显示使能

output TimeSet_EN;//时间调整与设置使能

output Stopwatch_EN;//秒钟功能使能

output Alarmclock_EN;//闹钟时间设置使能

output Date_EN;//时期显示使能

output DateSet_EN;//日期调整与设置使能

input SW3;//功能号选择

reg[7:0]led;

reg Timepiece_EN;

reg TimeSet_EN;

reg Stopwatch_EN;

reg Alarmclock_EN;

reg Date_EN;

reg DateSet_EN;

reg[2:0]Function;

always@(posedge SW3)/*实现对时间显示与调整，日期显示与调整，闹钟显示与调整，秒表操作等的控制*/begin//功能号的产生以及其自动循环

if(Function<3'b101)

Function<=Function+3'b1;

else

Function<=3'b0;

case(Function)//各个分功能的控制和实现

//时钟自动显示

3'b000:begin

led=8'b01111111;

Timepiece_EN<=1'b1;

TimeSet_EN<=1'b0;

Stopwatch_EN<=1'b0;

Alarmclock_EN<=1'b0;

Date_EN<=1'b0;

DateSet_EN<=1'b0;

end

//时钟调整与设置

3'b001:begin

led=8'b10111111;

Timepiece_EN<=1'b0;

TimeSet_EN<=1'b1;

Stopwatch_EN<=1'b0;

Alarmclock_EN<=1'b0;

Date_EN<=1'b0;

DateSet_EN<=1'b0;

end

//秒表

3'b010:begin

led=8'b11011111;

Timepiece_EN<=1'b0;

TimeSet_EN<=1'b0;

Stopwatch_EN<=1'b1;

Alarmclock_EN<=1'b0;

Date_EN<=1'b0;

DateSet_EN<=1'b0;

end

//闹钟时间设置

3'b011:begin

led=8'b11101111;

Timepiece_EN<=1'b0;

TimeSet_EN<=1'b0;

Stopwatch_EN<=1'b0;

Alarmclock_EN<=1'b1;

Date_EN<=1'b0;

DateSet_EN<=1'b0;

end

//日期显示

3'b100:begin

led=8'b11110111;

Timepiece_EN<=1'b0;

TimeSet_EN<=1'b0;

Stopwatch_EN<=1'b0;

Alarmclock_EN<=1'b0;

Date_EN<=1'b1;

DateSet_EN<=1'b0;

end

//日期调整与设置

3'b101:begin

led=8'b11111011;

Timepiece_EN<=1'b0;

TimeSet_EN<=1'b0;

Stopwatch_EN<=1'b0;

Alarmclock_EN<=1'b0;

Date_EN<=1'b0;

DateSet_EN<=1'b1;

enddefault:begin

led=8'b0;

Timepiece_EN<=1'b0;

TimeSet_EN<=1'b0;

Stopwatch_EN<=1'b0;

Alarmclock_EN<=1'b0;

Date_EN<=1'b0;

DateSet_EN<=1'b0;

end

endcase

end

endmodule

module fdiv(clk,f200Hz,f60Hz,f1Hz);

output f200Hz,f60Hz,f1Hz;

input clk;

reg f200Hz,f60Hz,f1Hz;

integer CNT1=0,CNT2=0,CNT3=0;

/*实现将全局时钟分频得到200Hz时钟信号*/

always@(posedge clk)

begin

if(CNT1<4)

begin

CNT1=CNT1+1;

f200Hz<=1'b0;

end

else

begin

CNT1=0;

f200Hz<=1'b1;

end

end

/*实现将200Hz时钟分频得到60Hz时钟信号*/

always@(posedge f200Hz)

begin

if(CNT2<2)

begin

CNT2=CNT2+1;

f60Hz<=1'b0;

endelse

begin

CNT2=0;

f60Hz<=1'b1;

end

end

/*实现将200Hz时钟分频得到1Hz时钟信号*/

always@(posedge f200Hz)

begin

if(CNT3<199)

begin

CNT3=CNT3+1;

f1Hz<=1'b0;

end

else

begin

CNT3=0;

f1Hz<=1'b1;

end

end

endmodule

module year_counter(EN,clk,year_data3,year_data2,year_data1,year_data0);

output[3:0]year_data3,year_data2,year_data1,year_data0;

input clk,EN;

reg[3:0]year_data3,year_data2,year_data1,year_data0;

reg E0;

always@(posedge clk)

begin

if(EN==1'b1)

begin

year_data3<=4'b0010;//年的最高位表示2

year_data2<=4'b0000;//年的第三位表示0

year_data1<=4'b0001;//年的第二位表示1

year_data0<=4'b0010;//年的最低位表示0

end

if(year_data0<4'b1001)//年的最低位小于9

year_data0<=year_data0+4'b1;//年的最低位进一

elsebegin

year_data0<=4'b0;//年的最低位清零

if(year_data1<4'b1001)//判断年的第二位是否大于9

year_data1<=year_data1+4'b1;//年的第二位表达方式

else

begin

year_data1<=4'b0;//年的第二位清零

if(year_data2<4'b1001)//判断年的第二位是否小于9

year_data2<=year_data2+4'b1;//年的第二位进一

else

begin

year_data2<=4'b0;//年的第二位清零

if(year_data3<4'b1001)//判断年的最高位是否小于9

year_data3<=year_data3+4'b1;//年的最高位进一

else

year_data3<=0;//清零

year_data2<=0;//清零

year_data1<=0;//清零

year_data0<=0;//清零

end

end

end

end

endmodulemodule date_counter(EN,clk,date_data1,date_data0,E0);

output[3:0]date_data1,date_data0;

output E0;

input clk,EN;

reg[3:0]date_data1,date_data0;

reg E0;

always@(posedge clk)

begin

if(EN==1'b1)

begin

if(date_data0<4'b1001)

date_data0<=date_data0+4'b1;

else

begin

E0<=1'b0;

date_data0<=4'b0;

if(date_data1<4'b00010)

date_data1<=date_data1+4'b1;

else

begin

date_data1<=4'b0;

E0<=1'b1;

endend

end

end

Endmodule

module month_counter(EN,clk,month_data1,month_data0,E0);

output[3:0]month_data1,month_data0;

output E0;

input clk,EN;

reg[3:0]month_data1,month_data0;

reg E0;

always@(posedge clk)

begin

if(EN==1'b1)

begin

month_data0<=4'b0001;

month_data1<=4'b0;

end

if(month_data0<4'b1001)

month_data0<=month_data0+4'b1;

else

begin

E0<=1'b0;

month_data0<=4'b0;

if(month_data1<4'b0001)

month_data1<=month_data1+4'b1;

else

begin

if((month_data1==4'b0001)&&(month_data0==4'b0010))

begin

month_data1<=4'b0;

month_data0<=4'b1;

E0<=1'b1;

end

end

end

end

Endmodule

module hour_counter(EN,clk,hour_data1,hour_data0,E0);

output[3:0]hour_data1,hour_data0;

output E0;

input clk,EN;

reg[3:0]hour_data1,hour_data0;

reg E0;

always@(posedge clk)

begin

if(EN==1'b1)

begin

if(hour_data0<4'b1001)

hour_data0<=hour_data0+4'b1;

else

begin

E0<=1'b0;

hour_data0<=4'b0;

if(hour_data1<4'b00010)

hour_data1<=hour_data1+4'b1;

else

begin

hour_data1<=4'b0;

E0<=1'b1;

end

end

end

end

Endmodule

module minute_counter(EN,clk,minute_data1,minute_data0,E0);

output[3:0]minute_data1,minute_data0;

output E0;

input clk,EN;

reg[3:0]minute_data1,minute_data0;

reg E0;

always@(posedge clk)

begin

if(EN==1'b1)begin

if(minute_data0<4'b1001)

minute_data0<=minute_data0+4'b1;

else

begin

E0<=1'b0;

minute_data0<=4'b0;

if(minute_data1<4'b0101)

minute_data1<=minute_data1+4'b1;

else

begin

minute_data1<=4'b0;

E0<=1'b1;

end

end

end

end

Endmodule

module second_counter(Timepiece_EN,clk,second_data1,second_data0,E0);

output[3:0]second_data1,second_data0;

output E0;

input clk,Timepiece_EN;

reg[3:0]second_data1,second_data0;

reg E0;

always@(posedge clk)

begin

if(Timepiece_EN==1'b1)

begin

if(second_data0<4'b1001)

second_data0<=second_data0+4'b1;

else

begin

E0<=1'b0;

second_data0<=4'b0;

if(second_data1<4'b0101)

second_data1<=second_data1+4'b1;

else

begin

second_data1<=4'b0;

E0<=1'b1;

endend

end

end

Endmodule