ACPL-331J中文注

ACPL-331J

1.5 Amp Output Current IGBT Gate Driver Optocoupler with Integrated (V CE ) Desaturation Detection, UVLO, Fault Status Feedback and Active Miller Clamping

Description

The ACPL-331J is an advanced 1.5 A output current, easy-to-use, intelligent gate driver which makes IGBT VCE fault protection compact, affordable, and easy-to implement. Features such as integrated V CE detection, under voltage lockout (UVLO), “soft” IGBT turn-off, isolated open collector fault feedback and active Miller clamping provide maximum design flexibility and circuit protec-tion.

The ACPL-331J contains a GaAsP LED. The LED is optically coupled to an integrated circuit with a power output stage. ACPL-331J is ideally suited for driving power IGBTs and MOSFETs used in motor control inverter applications. The voltage and current supplied by these optocouplers make them ideally suited for directly driving IGBTs with ratings up to 1200 V and 100 A. For IGBTs with higher ratings, the ACPL-331J can be used to drive a discrete power stage which drives the IGBT gate. The ACPL-331J has an insulation voltage of V IORM = 1 V PEAK .

Block Diagram

Features

• Under Voltage Lock-Out Protection (UVLO) with Hysteresis • Desaturation Detection • Miller Clamping

• Open Collector Isolated fault feedback • “Soft” IGBT Turn-off

• Fault Reset by next LED turn-on (low to high) after fault mute period • Available in SO-16 package

• Safety approvals: UL approved, 3750 V RMS for 1 minute, CSA approved, IEC/EN/DIN-EN 60747-5-2 approved V IORM = 1 V PEAK

Specifications

• 1.5 A maximum peak output current • 1.0 A minimum peak output current • 250 ns maximum propagation delay over temperature range

• 100 ns maximum pulse width distortion (PWD)• 15 kV/µs minimum common mode rejection (CMR) at V CM = 1500 V • I CC(max) < 5 mA maximum supply current • Wide V CC operating range: 15 V to 30 V over temperature range • 1.0 A Miller Clamp. Clamp pin short to V EE if not used • Wide operating temperature range: –40°C to 105°C

Applications

• Isolated IGBT/Power MOSFET gate drive • AC and brushless DC motor drives

• Industrial inverters and Uninterruptible Power Supply (UPS)

CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.

E

CC2

OUT CLAMP EE

LED

Pin Description

Pin

Symbol

Description

1V S Input Ground

2V CC1Positive input supply voltage. (4.5 V to 5.5 V)

3

FAULT

Fault output. FAULT changes from a high impedance state to a logic low output within 5 µs of the voltage on the DESAT pin exceeding an internal reference voltage of 6.5 V. FAULT output is an open collector which allows the FAULT outputs from all ACPL-331J in a circuit to be connected together in a “wired OR” forming a single fault bus for inter-facing directly to the micro-controller.4

V S Input Ground 5CATHODE Cathode 6ANODE Anode 7ANODE Anode 8CATHODE Cathode

9V EE Output supply voltage.10V CLAMP Miller clamp

11V OUT Gate drive voltage output 12V EE Output supply voltage.13V CC2Positive output supply voltage

14

DESAT

Desaturation voltage input. When the voltage on DESAT exceeds an internal reference voltage of 6.5 V while the IGBT is on, FAULT output is changed from a high impedance state to a logic low state within 5 µs.

15V LED

LED anode. This pin must be left unconnected for guaran-teed data sheet performance. (For optical coupling testing only)

16V E

Common (IGBT emitter) output supply voltage.

12345678

16151413

1211109

V E V LED DESAT V CC2V EE V OUT V CLAMP

V EE

V S V CC1FAULT V S

CATHODE ANODE ANODE CATHODE

Ordering Information

ACPL-331J is UL Recognized with 3750 Vrms for 1 minute per UL1577.

Part number

Option

Package

Surface Mount

Tape& Reel

IEC/EN/DIN EN 60747-5-2

Quantity

RoHS Compliant

ACPL-331J

-000E SO-16

X X 45 per tube -500E

X

X

X

850 per reel

To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1:

ACPL-331J-500E to order product of SO-16 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-2 Safety Approval in RoHS compliant.Example 2:

ACPL-331J-000E to order product of SO-16 Surface Mount package in tube packaging with IEC/EN/DIN EN 60747-5-2 Safety Approval and RoHS compliant.Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and RoHS compliant option will use ‘-XXXE‘.

Dimensions in inches (millimeters)

Notes: Initial and continued variation in the color of the ACPL-331J’s white mold compound is normal and does note affect device performance or reliability.

Floating Lead Protrusion is 0.25 mm (10 mils) max.

ACPL-331J 16-Lead Surface Mount Package

Package Outline Drawings

0.050TYPE NUMBER DATE CODE

LAND PATTERN RECOMMENDATION

Solder Reflow Thermal Profile

Recommended Pb-Free IR Profile

Note: Non-halide flux should be used.

TIME (SECONDS)

T E M P E R A T U R E (°C )

ROOM Note: Non-halide flux should be used.

NO TES:

THE TIME FROM 25°C to PEAK TEMPERATURE = 8 MINUTES MAX.T smax = 200 °C, T smin = 150°C

Table 1. IEC/EN/DIN EN 60747-5-2 Insulation Characteristics*

Description

Symbol Characteristic

Unit

Installation classification per DIN VDE 0110/1., Table 1 for rated mains voltage ≤ 150 V rms for rated mains voltage ≤ 300 V rms for rated mains voltage ≤ 600 V rms I – IV I – IV I – III Climatic Classification

55/100/21Pollution Degree (DIN VDE 0110/1.)2Maximum Working Insulation Voltage

V IORM 1V peak Input to Output Test Voltage, Method b**,

V IORM x 1.875=V PR , 100% Production Test with t m =1 sec, Partial discharge < 5 pC

V PR

1670

V peak

Input to Output Test Voltage, Method a**,

V IORM x 1.5=V PR , Type and Sample Test, t m =60 sec, Partial discharge < 5 pC V PR 1336V peak Highest Allowable Overvoltage (Transient Overvoltage t ini = 10 sec)V IOTM

6000

V peak

Safety-limiting values – maximum values allowed in the event of a failure Case Temperature T S 175°C Input Current I S, INPUT 400mA Output Power

P S, OUTPUT 1200mW Insulation Resistance at T S , V IO = 500 V

R S

>109

W

* Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application. Surface mount classification is class A in accordance with CECCOO802.

** Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section IEC/EN/DIN EN 60747-5-2, for a detailed description of Method a and Method b partial discharge test profiles.Dependence of Safety Limiting Values on Temperature. (take from DS AV01-0579EN Pg.7)

Regulatory Information

The ACPL-331J is approved by the following organizations:

UL

Approval under UL 1577, component recognition program up to VISO = 3750 VRMS. File E55361.

CSA

Approval under CSA Component Acceptance Notice #5, File CA 88324.

IEC/EN/DIN EN 60747-5-2

Approval under:

IEC 60747-5-2 :1997 + A1:2002 EN 60747-5-2:2001 + A1:2002

DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01

S P - P O W E R - m W

0S

T - CASE TEMPERATURE - °C 120080014004002006001000

Table 2. Insulation and Safety Related Specifications

Parameter

Symbol

ACPL-331J

Units

Conditions

Minimum External Air Gap (Clearance)L(101)8.3Mm Measured from input terminals to output terminals, shortest distance through air.

Minimum External Tracking (Creepage)L(102)

8.3Mm Measured from input terminals to output terminals, shortest distance path along body.

Minimum Internal Plastic Gap (Internal Clearance)

0.5

Mm

Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector.Tracking Resistance (Comparative Tracking Index)CTI

>175V

DIN IEC 112/VDE 0303 Part 1

(<1 µs pulse width, 300pps)F(TRAN)Table 4. Recommended Operating Conditions

Parameter

Symbol

Min.

Max.

Units

Note

Operating Temperature T A

- 40105°C 2Total Output Supply Voltage (V CC2 - V EE )1530V 7Negative Output Supply Voltage (V E - V EE )015

V 4

Positive Output Supply Voltage (V CC2 - V E )1530 - (V E - V EE )V Input Current (ON)I F(ON)812mA Input Voltage (OFF)V F(OFF)

- 3.6

0.8

V

Unless otherwise noted, all typical values at T A = 25°C, V CC2 - V EE = 30 V, V E - V EE = 0 V;

all Minimum/Maximum specifications are at Recommended Operating Conditions.Parameter

Symbol

Min.Typ.

Max.

Units

Test Conditions

Fig.Note

FAULT Logic Low Output Voltage V FAULTL 0.10.4V I FAULT = 1.1 mA, V CC1 = 5.5V 0.10.4V I FAULT = 1.1 mA, V CC1 = 3.3V FAULT Logic High Output Current I FAULTH 0.020.5µA V FAULT = 5.5 V, V CC1 = 5.5V 0.002

0.3

µA V FAULT = 3.3 V, V CC1 = 3.3V High Level Output Current I OH -0.3-0.75A V O = V CC2 – 44, 185-1.0A V O = V CC2 – 153Low Level

Output Current

I OL 0.30.75A V O = V EE + 2.55, 19

51.0A

V O = V EE + 153Output Voltage OH CC CC O 2023

Low Level

Output Voltage V OL 0.170.5

V I O = 100 mA

3, 5, 21

Clamp Pin Threshold Voltage V tClamp 2.0

V

Unless otherwise noted, all typical values at T A = 25°C, V CC2 - V EE = 30 V, V E - V EE = 0 V;

all Minimum/Maximum specifications are at Recommended Operating Conditions.Duty Cycle = 50%,I F = 10 mA, V CC2 = 30 V

13, 26

Propagation Delay Time t PHL 100180250ns 14, 17PHL PLH 17, 16

R Fall Time

t F

50ns DESAT Sense to 90% VO Delay

t DESAT(90%)

0.15

0.3

µs

C DESAT = 100pF, R F =2.1kΩ, R g = 20 W , C g = 5 nF, V CC2 = 30 V

14, 27, 3419

DESAT Sense to 10% VO Delay t DESAT(10%) 1.1 1.5µs

C DESAT = 100pF, R F =2.1kΩ , R g = 20 W , C g = 5 nF, V CC2 = 30 V 15, 16, 17, 27, 34DESAT Sense to Low Level FAULT Signal Delay

t DESAT(FAULT)0.250.5µs

C DESAT = 100pF, R F = 2.1 k W ,

R g = 20 W , C g = 5 nF, V CC2 = 30 V

27, 34

18DESAT Sense to DESAT Low Propagation Delay

t DESAT(LOW)0.25µs C DESAT = 100pF, R F = 2.1 k W ,

R g = 20 W , C g = 5 nF, V CC2 = 30 V

27, 3419

DESAT Input Mute t DESAT(MUTE)5µs 3420

RESET to High Level FAULT Signal Delay

t RESET(FAULT)

0.3

1

2.0

µs

C DESAT = 100pF,R F = 2.1 k W ,

Rg = 20 W , Cg = 5 nF,V CC1 = 5.5V, V CC2 = 30 V 0.8 1.5 2.5µs

C DESAT = 100pF, R F = 2.1 k W ,

Rg = 20 W , Cg = 5 nF,V CC1 = 3.3V, V CC2 = 30 V Mode Transient Immunity

L A F V CM = 1500 V, V CC2 = 30 V

30, 31

Notes:

1. Derate linearly above 70°C free air temperature at a rate of 0.3 mA/°C.

2. In order to achieve the absolute maximum power dissipation specified, pins 4, 9, and 10 require ground plane connections and may require

airflow. See the Thermal Model section in the application notes at the end of this data sheet for details on how to estimate junction temperature and power dissipation. In most cases the absolute maximum output IC junction temperature is the limiting factor. The actual power dissipation achievable will depend on the application environment (PCB Layout, air flow, part placement, etc.). See the Recommended PCB Layout section in the application notes for layout considerations. Output IC power dissipation is derated linearly at 10 mW/°C above 90°C. Input IC power dissipation does not require derating.

3. Maximum pulse width = 10 µs. This value is intended to allow for component tolerances for designs with IO peak minimum = 1.0 A.

Derate linearly from 2.0 A at +25°C to 1.5 A at +105°C. This compensates for increased I OPEAK due to changes in V OL over temperature.4. This supply is optional. Required only when negative gate drive is implemented.5. Maximum pulse width = 50 µs.

6. See the Slow IGBT Gate Discharge During Fault Condition section in the applications notes at the end of this data sheet for further details.

7. 15 V is the recommended minimum operating positive supply voltage (V CC2 - V E ) to ensure adequate margin in excess of the maximum V UVLO+

threshold of 12.5 V. For High Level Output Voltage testing, V OH is measured with a dc load current. When driving capacitive loads, V OH will approach V CC as I OH approaches zero units.8. Maximum pulse width = 1.0 ms.

9. Once V O of the ACPL-331J is allowed to go high (V CC2 - V E > V UVLO ), the DESAT detection feature of the ACPL-331J will be the primary source of

IGBT protection. UVLO is needed to ensure DESAT is functional. Once V UVLO+ > 12.5 V, DESAT will remain functional until V UVLO- < 9.2 V. Thus, the DESAT detection and UVLO features of the ACPL-331J work in conjunction to ensure constant IGBT protection.

10. See the DESAT fault detection blanking time section in the applications notes at the end of this data sheet for further details.11. This is the “increasing” (i.e. turn-on or “positive going” direction) of V CC2 - V E 12. This is the “decreasing” (i.e. turn-off or “negative going” direction) of V CC2 - V E 13. This load condition approximates the gate load of a 1200 V/75A IGBT.14. Pulse Width Distortion (PWD) is defined as |t PHL - t PLH | for any given unit.15. As measured from I F to V O .

16. The difference between t PHL and t PLH between any two ACPL-331J parts under the same test conditions.17. As measured from ANODE, CATHODE of LED to V OUT

18. This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes low.

19. This is the amount of time the DESAT threshold must be exceeded before VOUT begins to go low, and the FAULT output to go low. This is supply

voltage dependent.

20. Auto Reset: This is the amount of time when VOUT will be asserted low after DESAT threshold is exceeded. See the Description of Operation

(Auto Reset) topic in the application information section.

21. Common mode transient immunity in the high state is the maximum tolerable dV CM /dt of the common mode pulse, V CM , to assure that the

output will remain in the high state (i.e., V O > 15 V or FAULT > 2 V). A 100 pF and a 2.1 kΩ pull-up resistor is needed in fault detection mode.

22. Common mode transient immunity in the low state is the maximum tolerable dV CM /dt of the common mode pulse, V CM , to assure that the

output will remain in a low state (i.e., V O < 1.0 V or FAULT < 0.8 V).

23. To clamp the output voltage at V CC - 3 VBE , a pull-down resistor between the output and V EE is recommended to sink a static current of 650 µA

while the output is high. See the Output Pull-Down Resistor section in the application notes at the end of this data sheet if an output pull-down resistor is not used.

Figure 1. Timing Curve

-2.5-2-1.5-1-0.50

-40

-20020406080

105

T A -TEMPERATURE -o C

(V O H -V C C )-H I G H O U T P U T V O L T A G E D R O P -V

Figure 2. V OH vs. temperature

Figure 3. V OL vs. temperature

Figure 4. V OH vs. IOH Figure 5. V OL vs. I OL

28.0

28.529.0

29.5

30.0

00.20.40.60.81

I OH -OUTPUT HIGH CURRENT -

A

(V O H -V C C )-H I G H O U T P U T V O L T A G E D R O P -V

00.51 1.5

I OL -OUTPUT LOW CURRENT -A

V O L -O U T P U T L O W V O L T A G E -

V

00.050.10.150.20.25

-40

-200204060

80105

V O L -O U T P U T L O

W V O

L T A G E -V

T A -TEMPERATURE -

o C

Figure 7. I CC2 vs. V

CC2

-0.35

-0.30

-0.25

-0.20

-40

-20

20

40

60

80

105

T A -TEMPERATURE -o C

I C H -B L A N K I N G C A P A C I T O R C H A R G I N G C U R R E N T -m A

Figure 8. I CHG

vs. temperature 6.06.5

7.0

7.5

-40

-20

20

40

60

80105

T A -TEMPERATURE -

o C

V D E S A T -D E S A T T H R E S H O L D -V

100150200250

300

-40

-20

20

40

60

80

105

T A -TEMPERATURE -o

C

T P -P R O P A G A T I O N D E L A Y -n s

Figure 9. DESAT threshold vs. temperature

Figure 10. Propagation delay vs. temperature 100

150

200

250

300

15

202530

Vcc - SUPPLY VOLTAGE - V

T P - P R O P A G A T I O N D E L A Y - n s

Figure 11. Propagation delay vs. supply voltage

2.00

2.252.502.75

3.003.253.50

I C C 2-O U T P U T S U P P L Y C U R R E N T -m A

Figure 6. I CC2 vs. temperature 2.25

2.35

2.45

2.55

2.65

15

20

25

30

I C C 2 - O U T P U T S U P P L Y C U R R E N T - m A

V CC2 - SUPPLY VOLTAGE - V

Figure 13. Propagation delay vs. load capacitance

100

200

300

10

20

30

40

50

LOAD CAPACITANCE - nF

T P - P R O P A G A T I O N D E L A Y - n

s

100150

200

250-40

-20020406080105

T A -TEMPERATURE -o C T D E S A T 90%-D E S A T S e n s e t o 90%V o D e l a y -n s

Figure 14. DESAT sense to 90% V OUT delay vs. temperature

-40

-20020406080105

T A -TEMPERATURE -o C

T D E S A T 10%-D E S A T S e n s e t o 10%V o D e l a y -n s

Figure 15. DESAT sense to 10% V OUT

delay vs. temperature

0.01.0

2.0

3.0

4.0

10

20

3040

50

LOAD RESISTANCE-ohm

T D E S A T 10% - D E S A T S e n s e t o 10% V o D e l a y - n s

Figure 16. DESAT sense to 10% V OUT delay vs. load resistance 0.000

0.004

0.008

0.012

010********

LOAD CAPACITANCE-nF

T D E S A T 10% - D E S A T S e n s e

t o 10% V o D e l a y - n s

Figure 17. DESAT sense to 10% V OUT delay vs. load capacitance

100

150

200

250

300010

2030

4050

LOAD RESISTANCE - ohm

T P - P R O P A G A T I O N D E L A Y - n s

Figure 12. Propagation delay vs. load resistance

Figure 18. I OH Pulsed test circuit

Figure 19. I OL Pulsed test circuit

Figure 20. V OH Pulsed test circuit

Figure 21. V OL Pulsed test circuit

Figure 22. I CC2H test circuit

Figure 23. I CC2L test circuit

Figure 24. I CHG Pulsed test circuit

Figure 25. I DSCHG test circuit

Figure 26. t PLH , t PHL , t f , t r , test circuit

Figure 27. tDESAT fault test circuit

Figure 28. CMR Test circuit LED2 off

V

V CM

Figure 30. CMR Test circuit LED1 off

V CM

Figure 31. CMR Test Circuit LED1 on

V CM

Application Information Product Overview Description

The ACPL-331J is a highly integrated power control device that incorporates all the necessary components for a complete, isolated IGBT / MOSFET gate drive circuit with fault protection and feedback into one SO-16 package. Active Miller clamp function eliminates the need of negative gate drive in most application and allows the use of simple bootstrap supply for high side driver. An optically isolated power output stage drives IGBTs with power ratings of up to 100 A and 1200 V. A high speed internal optical link minimizes the propagation delays between the microcontroller and the IGBT while allowing the two systems to operate at very large common mode voltage differences that are common in industrial motor drives and other power switching applications. An output IC provides local protection for the IGBT to prevent damage during over current, and a second optical link provides a fully isolated fault status feedback signal for the microcontroller. A built in “watchdog” circuit, UVLO monitors the power stage supply voltage to prevent IGBT caused by insufficient gate drive voltages. This integrated IGBT gate driver is designed to increase the performance and reliability of a motor drive without the cost, size, and complexity of a discrete design.

Two light emitting diodes and two integrated circuits housed in the same SO-16 package provide the input control circuitry, the output power stage, and two optical channels. The output Detector IC is designed manufac-tured on a high voltage BiCMOS/Power DMOS process. The forward optical signal path, as indicated by LED1, transmits the gate control signal. The return optical signal path, as indicated by LED2, transmits the fault status feedback signal.

Under normal operation, the LED1 directly controls the IGBT gate through the isolated output detector IC, and LED2 remains off. When an IGBT fault is detected, the output detector IC immediately begins a “soft” shutdown sequence, reducing the IGBT current to zero in a con-trolled manner to avoid potential IGBT damage from inductive over voltages. Simultaneously, this fault status is transmitted back to the input via LED2, where the fault latch disables the gate control input and the active low fault output alerts the microcontroller.

During power-up, the Under Voltage Lockout (UVLO) feature prevents the application of insufficient gate voltage to the IGBT, by forcing the ACPL-331J’s output low. Once the output is in the high state, the DESAT (V CE ) detection feature of the ACPL-331J provides IGBT pro-tection. Thus, UVLO and DESAT work in conjunction to provide constant IGBT protection.

Recommended Application Circuit

The ACPL-331J has an LED input gate control, and an open collector fault output suitable for wired ‘OR’ ap-plications. The recommended application circuit shown in Figure 33 illustrates a typical gate drive implementa-tion using the ACPL-331J. The following describes about driving IGBT. However, it is also applicable to MOSFET. Depending upon the MOSFET or IGBT gate threshold re-quirements, designers may want to adjust the VCC supply voltage (Recommended V CC = 17.5V for IGBT and 12.5V for MOSFET).

The two supply bypass capacitors (0.1 µF) provide the large transient currents necessary during a switching transition. Because of the transient nature of the charging currents, a low current (5mA) power supply suffices. The desaturation diode D DESAT 600V/1200V fast recovery type, t rr below 75ns (e.g. ERA34-10) and capacitor C BLANK are necessary external components for the fault detection circuitry. The gate resistor R G serves to limit gate charge current and controls the IGBT collector voltage rise and fall times. The open collector fault output has a passive pull-up resistor R F (2.1 k W ) and a 330 pF filtering capacitor, C F . A 47 k W pull down resistor R PULL-DOWN on V OUT provides a predictable high level output voltage (V OH ). In this application, the IGBT gate driver will shut down when a fault is detected and fault reset by next cycle of IGBT turn on. Application notes are mentioned at the end of this datasheet.

Figure 32. Block Diagram of ACPL-331J

E

CC2

OUT CLAMP EE

LED

Figure 33. Recommended application circuit (Single Supply) with desaturation detection and active Miller Clamp

Description of Operation Normal Operation

During normal operation, V OUT of the ACPL-331J is con-trolled by input LED current I F (pins 5, 6, 7 and 8), with the IGBT collector-to-emitter voltage being monitored through D DESAT . The FAULT output is high. See Figure 34.

Fault Condition

The DESAT pin monitors the IGBT Vce voltage. When the voltage on the DESAT pin exceeds 6.5 V while the IGBT is

Figure 34. Fault Timing diagramactivated is an internal feedback channel which brings the FAULT output low for

the purpose of notifying the micro-controller of the fault condition.

Fault Reset

Once fault is detected, the output will be muted for 5 μs (minimum). All input LED signals will be ignored during the driver to completely soft + HVDC

-HVDC

AC

Output Control

The outputs (V OUT and FAULT) of the ACPL-331J are con-trolled by the combination of I F , UVLO and a detected IGBT Desat condition. Once UVLO is not active (V CC2 - V E > V UVLO ), V OUT is allowed to go high, and the DESAT (pin 14) detection feature of the ACPL-331J will be the primary source of IGBT protection. UVLO is needed to ensure DESAT is functional. Once V UVLO+ > 10.5V, DESAT will remain functional until V UVLO- < 11.1V. Thus, the DESAT detection and UVLO features of the ACPL-331J work in conjunction to ensure constant IGBT protection.

Desaturation Detection and High Current Protection

The ACPL-331J satisfies these criteria by combining a high speed, high output current driver, high voltage optical isolation between the input and output, local IGBT desaturation detection and shut down, and an optically isolated fault status feedback signal into a single 16-pin surface mount package.

The fault detection method, which is adopted in the ACPL-331J is to monitor the saturation (collector) voltage of the IGBT and to trigger a local fault shutdown sequence if the collector voltage exceeds a predeter-mined threshold. A small gate discharge device slowly reduces the high short circuit IGBT current to prevent damaging voltage spikes. Before the dissipated energy can reach destructive levels, the IGBT is shut off. During the off state of the IGBT, the fault detect circuitry is simply disabled to prevent false ‘fault’ signals.

The alternative protection scheme of measuring IGBT current to prevent desaturation is effective if the short circuit capability of the power device is known, but this method will fail if the gate drive voltage decreases enough to only partially turn on the IGBT. By directly measuring the collector voltage, the ACPL-331J limits the power dissipation in the IGBT even with insufficient gate drive voltage. Another more subtle advantage of the desaturation detection method is that power dissipation in the IGBT is monitored, while the current sense method relies on a preset current threshold to predict the safe limit of operation. Therefore, an overly conservative over current threshold is not needed to protect the IGBT.

I F

UVLO (V CC2 – V E )

Desat Condition Detected on Pin 14

Pin 3 (FAULT) Output

V OUT

X Active X X Low X X Yes Low Low OFF X X X Low ON

Not Active

No

High

High

Slow IGBT Gate Discharge during Fault Condition

When a desaturation fault is detected, a weak pull-down device in the ACPL-331J output drive stage will turn on to ‘softly’ turn off the IGBT. This device slowly discharges the IGBT gate to prevent fast changes in drain current that could cause damaging voltage spikes due to lead and wire inductance. During the slow turn off, the large output pull-down device remains off until the output voltage falls below V EE + 2 Volts, at which time the large pull down device clamps the IGBT gate to V EE .

DESAT Fault Detection Blanking Time

The DESAT fault detection circuitry must remain disabled for a short time period following the turn-on of the IGBT to allow the collector voltage to fall below the DESAT threshold. This time period, called the DESAT blanking time is controlled by the internal DESAT charge current, the DESAT voltage threshold, and the external DESAT capacitor.

The nominal blanking time is calculated in terms of external capacitance (C BLANK ), FAULT threshold voltage (V DESAT ), and DESAT charge current (I CHG ) as t BLANK = C BLANK x V DESAT / I CHG . The nominal blanking time with the recommended 100pF capacitor is 100pF * 6.5 V / 240 µA = 2.7 µsec.

The capacitance value can be scaled slightly to adjust the blanking time, though a value smaller than 100 pF is not recommended. This nominal blanking time represents the longest time it will take for the ACPL-331J to respond to a DESAT fault condition. If the IGBT is turned on while the collector and emitter are shorted to the supply rails (switching into a short), the soft shut-down sequence will begin after approximately 3 µsec. If the IGBT collector and emitter are shorted to the supply rails after the IGBT is already on, the response time will be much quicker due to the parasitic parallel capacitance of the DESAT diode. The recommended 100pF capacitor should provide adequate blanking as well as fault response times for

most applications.

Figure 35. Output pull-down resistor.

DESAT Pin Protection Resistor

The freewheeling of flyback diodes connected across the IGBTs can have large instantaneous forward voltage transients which greatly exceed the nominal forward voltage of the diode. This may result in a large negative voltage spike on the DESAT pin which will draw substan-tial current out of the driver if protection is not used. To limit this current to levels that will not damage the driver IC, a 100 ohm resistor should be inserted in series with the DESAT diode. The added resistance will not alter the DESAT threshold or the DESAT blanking time.

Figure 36. DESAT pin protection.

Under Voltage Lockout

The ACPL-331J Under Voltage Lockout (UVLO) feature is designed to prevent the application of insufficient gate voltage to the IGBT by forcing the ACPL-331J output low during power-up. IGBTs typically require gate voltages of 15 V to achieve their rated V CE(ON) voltage. At gate voltages below 13 V typically, the V CE(ON) voltage increases dramatically, especially at higher currents. At very low gate voltages (below 10 V), the IGBT may operate in the linear region and quickly overheat. The UVLO function causes the output to be clamped whenever in-sufficient operating supply (V CC2) is applied. Once V CC2 exceeds V UVLO+ (the positive-going UVLO threshold), the UVLO clamp is released to allow the device output to turn on in response to input signals. As V CC2 is increased from 0 V (at some level below V UVLO+), first the DESAT protec-tion circuitry becomes active. As V CC2 is further increased (above V UVLO+), the UVLO clamp is released. Before the time the UVLO clamp is released, the DESAT protection is already active. Therefore, the UVLO and DESAT Fault detection feature work together to provide seamless pro-tection regardless of supply voltage (V CC2).

Active Miller Clamp

A Miller clamp allows the control of the Miller current during a high dV/dt situation and can eliminate the use of a negative supply voltage in most of the applications. During turn-off, the gate voltage is monitored and the clamp output is activated when gate voltage goes below 2V (relative to V EE ). The clamp voltage is V OL +2.5V typ for a Miller current up to 1100mA. The clamp is disabled when the LED input is triggered again.

Other Recommended Components

The application circuit in Figure 33 includes an output pull-down resistor, a DESAT pin protection resistor, a FAULT pin capacitor, and a FAULT pin pullup resistor and Active Miller Clamp connection.

Output Pull-Down Resistor

During the output high transition, the output voltage rapidly rises to within 3 diode drops of V CC2. If the output current then drops to zero due to a capacitive load, the output voltage will slowly rise from roughly V CC2-3(V BE ) to V CC2 within a period of several microseconds. To limit the output voltage to V CC2-3(V BE ), a pull-down resistor, R PULL-DOWN between the output and V EE is recommended to sink a static current of several 650 µA while the output is high. Pull-down resistor values are dependent on the amount of positive supply and can be adjusted according to the formula, R pull-down = [V CC2-3 * (V BE )] / 650 µA.

Pull-up Resistor on FAULT Pin

The FAULT pin is an open collector output and therefore requires a pull-up resistor to provide a high-level signal. Also the FAULT output can be wire ‘OR’ed together with other types of protection (e.g. over-temperature, over-voltage, over-current ) to alert the microcontroller.

Figure 38. Large IGBT drive with negative gate drive, external booster. V CLAMP control secondary discharge path for higher power application.

Figure 37. IGBT drive with negative gate drive, external booster and desaturation detection (V CLAMP should be connected to V EE when it is not used) V CLAMP is used as secondary gate discharge path. * indicates component required for negative gate drive topology

Other Possible Application Circuit (Output Stage)

+ HVDC

-HVDC

AC

+ HVDC

-HVDC

AC

Capacitor on FAULT Pin for High CMR

Rapid common mode transients can affect the fault pin voltage while the fault output is in the high state. A 330 pF capacitor should be connected between the fault pin and ground to achieve adequate CMOS noise margins at the specified CMR value of 15 kV/µs. The added capaci-tance does not increase the fault output delay when a desaturation condition is detected.

AN5314 – Active Miller Clamp

AN5324 - Desaturation Fault Detection

AN5315 – “Soft” Turn-off Feature

AN1087 – Thermal Data for Optocouplers

AN1043 – Common-Mode Noise : Sources and Solutions

AN02-0310EN - Plastics Optocoupler Product ESD and Moisture Sensitivity

For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2008 Avago Technologies. All rights reserved.

AV02-0119EN - November 6, 2008