verilog--4路抢答器设计-带30s倒计时

一、程序

module qiangda4(clr,clk,input1,input2,input3,input4,seg,clockin,scan,LED);

input clr,clk,input1,input2,input3,input4;

    output [7:0] seg;   //7段数码管数据

    output [7:0] scan;   //数码管位选

    output [3:0] LED;    //输出LED灯指示

    output clockin;      //蜂鸣器

    reg [7:0] seg;

    reg [7:0] scan;

    reg [3:0] LED;

    reg clockin;

    reg [3:0] data;

    reg input_flag,count_flag;

    reg [14:0] count1;

    reg [8:0] count2;

    reg [3:0] LED_N;

    //reg clock_flag;

    reg div1khz,div1hz;

    reg [2:0] cnt;

    reg [3:0] dat;

    //reg [7:0] data_count;

    reg [3:0] count_one,count_ten;

    initial count_one='d0;     //初始化

    initial count_ten='d3;

    initial data=4'b0000;

    initial LED_N=4'b1111;

//-------------fenping分频1khz-----------------------------------    

always @(posedge clk )

begin 

    if(count1=='d25000)

     begin div1khz<=~div1khz;count1<=0;end

    else

     begin count1<=count1+1'b1;end

end

//-------------fenping--1hz-------------------------------

always @(posedge div1khz)

begin

    if(count2=='d500)

     begin div1hz<=~div1hz;count2<=0;end

    else

     begin count2<=count2+1'b1;end

end

//----------------------------------------------------------

always @(posedge div1hz or negedge clr)

begin

    if(!clr)

        begin 

         count_one<='d0;count_ten<='d3;count_flag<=1'b0;

        end

    else if((!input_flag)&(!count_flag))

             begin if(count_one=='d0&&count_ten=='d0)

                 begin count_flag<=1'b1;

                       end

                   else if(count_one=='d0) 

                 begin count_one<=4'b1001;

                             count_ten<=count_ten-1'b1;

                            end

                        else 

                 begin count_one<=count_one-1'b1;

                            end

        end

        else 

         begin count_one<=count_one;

             count_ten<=count_ten;

            end      

end              

//-----------------------------------------------------------

always @(posedge clk )     //or input1 or input2 or input3 or input4

begin

    if(!clr)

    begin 

     LED_N<=4'b1111;

     //clock_flag<=1'b0;

     input_flag<=1'b0;

     data<=4'b0000;

    end 

    else if((!input_flag)&(!count_flag))

         begin     

             if(input1==0)

             begin 

             data<=4'b0001;

             LED_N<=4'b0111;

             input_flag<=1'b1;

             end

             else if(input2==0)

                  begin

             data<=4'b0010;

             LED_N<=4'b1011;

             input_flag<=1'b1;

                  end

                  else if(input3==0)

                       begin 

                 data<=4'b0011;

                         LED_N<=4'b1101;

                         input_flag<=1'b1;

                       end

                       else if(input4==0)

                            begin   

                         data<=4'b0100;

                             LED_N<=4'b1110;

                         input_flag<=1'b1;

                            end

                            else 

                                begin 

                                 data<=data;

                                 LED_N<=LED_N;

                                 input_flag<=input_flag;

                                end

         end

end

//-------------led灯及蜂鸣器---------------------------------------------------

always @(posedge clk)

begin

LED<=LED_N;

clockin<=div1khz&(input_flag|count_flag);

//dat<=data;

end

//--------------shu ma guan sao miao数码管扫描---------------------------------

always @(posedge div1khz)

begin

    if(cnt=='d3)

     begin cnt<=0;end

    else

begin cnt<=cnt+1'b1;end

end

//-----------------------------------------------------

always @(cnt,data,count_one,count_ten)

begin 

    case(cnt)

//3'b000 : begin scan<=8'b01111111;end

3'b001 : begin scan<=8'b10111111;dat<=data;end //选手编号

3'b010 : begin scan<=8'b11011111;dat<=count_one;end   //倒计时

3'b011 : begin scan<=8'b11101111;dat<=count_ten;end

default : begin scan<=8'bx;dat<=4'bx;end

    endcase

end

//--------------------------------------------------------

always @(dat)    

begin

    case(dat)

4'b0000 : seg[7:0]<=8'b11000000;

4'b0001 : seg[7:0]<=8'b11111001;

4'b0010 : seg[7:0]<=8'b10100100;

4'b0011 : seg[7:0]<=8'b10110000;

4'b0100 : seg[7:0]<=8'b10011001;

4'b0101 : seg[7:0]<=8'b10010010;

4'b0110 : seg[7:0]<=8'b10000010;

4'b0111 : seg[7:0]<=8'b11111000;

4'b1000 : seg[7:0]<=8'b10000000;

4'b1001 : seg[7:0]<=8'b10010000;

4'b1010 : seg[7:0]<=8'b10001000;

4'b1011 : seg[7:0]<=8'b10000011;

4'b1100 : seg[7:0]<=8'b11000110;

4'b1101 : seg[7:0]<=8'b10100001;

4'b1110 : seg[7:0]<=8'b10000110;

4'b1111 : seg[7:0]<=8'b10001110;

default : seg[7:0]<=8'bx;

    endcase

end

endmodule                    

二、框图

三、设计思路

     四路抢答，有30s倒计时，当有人抢答时，数码管显示对应选手编号，同时对应LED灯亮，蜂鸣器响起，此时其他选手抢答无效。当倒计时到达0时，蜂鸣器响，此时不能够抢答，清零后重新计时。

     程序有个小问题，数码管显示选手编号时，存在干扰，能够勉强辨认出选手编号，但不够清晰，找了好久都没查出。