LVDS specification

In the CMS inner tracker readout system the distribution of the clock (CLK) and trigger (T1) signals will be made using twisted pair copper cables. These cables will be driven by the PPLDelay IC which will use Low Voltage Differential Signaling (LVDS) for signal transmission. The trigger and clock LVDS signals generated by PLLDelay IC will interface directly with the APV and the CCU ASICS. LVD signaling will also be used to interface the PLLDelay IC with the optical receiver which provides the CLK-T1 signal form where the clock and first-level trigger signals are derived. Additionally, data and clock signals will be transmitted between the different CCU modules using LVD signaling. In this note the LVDS interface between the different system components is specified following the IEEE 1596.3 SCI-LVDS standard.

LVDS

In LVDS the transmission signals are modulated on the transmission media as an electrical low amplitude differential signal (400mV). The media is either a coaxial cable or a twisted pair cable with a well defined characteristic impedance. The line driver is a constant current mode driver that provides a 4mA (nominal) output current to the transmission media. Since the transmission cable is terminated to v Ãpuh hp r v vpÃv rqh prà vphyy Ã

Driver

Electrical Specifications1,2

Symbol Parameter Min Target Max Units V OD Differential output voltage250400450mV V OS Offset voltage 1.125 1.2 1.375V V OH Output voltage high 1.4 1.6V V OL Output voltage low0.9 1.0V Switching Specifications 1,3

Symbol Parameter Min Target Max Units t r Rise time (20% to 80%)0.4 1.5ns t f Fall time (20% to 80%)0.4 1.5ns t sk Differential skew4400ps

t pw Pulse width distortion5200

ps

)

Receiver

Electrical Specifications

Symbol Parameter Min Target Max

Units

V TH Differential input high threshold+100mV V TL Differential input low threshold-100mV V CM Common mode range6±1±1.2V

I IN Input current-1010uA

1 Refer to Figure

2 for symbols definitions.

2ÃT rpvsvph v Ãs Ã

Ãh qÃ8L = 5pF.

4 Skew measured at the 50% point of the transition: t

sk

=|t LH(D out+)-t HL(D out-)| or t sk=|t LH(D out-)-

t HL(D out+)|.

5 Pulse width distortion measured at 0V differential:

6 Around the nominal 1.2V common mode voltage