1.3w音频功率放大器

1.3 Watt Audio Power Amplifier with Fast Turn On Time

The NCP2990 is an audio power amplifier designed for portable communication device applications such as mobile phone

applications. The NCP2990 is capable of delivering 1.3 W of continuous average power to an 8.0 W BTL load from a 5.0 V power supply, and 1.0 W to a 4.0W BTL load from a 3.6 V power supply. The NCP2990 provides high quality audio while requiring few external components and minimal power consumption. It features a low−power consumption shutdown mode, which is achieved by driving the SHUTDOWN pin with logic low.

The NCP2990 contains circuitry to prevent from “pop and click”noise that would otherwise occur during turn−on and turn−off transitions. It is a zero pop noise device when a single ended audio input is used.

For maximum flexibility, the NCP2990 provides an externally controlled gain (with resistors), as well as an externally controlled turn−on time (with the bypass capacitor). When using a 1 m F bypass capacitor, it offers 60 ms wake up time.

Due to its superior PSRR, it can be directly connected to the battery, saving the use of an LDO.

This device is available in a 9−Pin Flip−Chip CSP (Lead−Free).

Features

•1.3 W to an 8.0 W BTL Load from a 5.0 V Power Supply •Superior PSRR: Direct Connection to the Battery

•Zero Pop Noise Signature with a Single Ended Audio Input •Ultra Low Current Shutdown Mode: 10 nA

•2.2 V−5.5 V Operation

•External Gain Configuration Capability

•External Turn−on Time Configuration Capability:

60 ms (1 m F Bypass Capacitor)

•Up to 1.0 nF Capacitive Load Driving Capability •Thermal Overload Protection Circuitry

•This is a Pb−Free Device*

Typical Applications

•Portable Electronic Devices

•PDAs

•Wireless Phones

*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting T echniques Reference Manual, SOLDERRM/D.

See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet.

ORDERING INFORMATION

http://onsemi.com

Figure 1. Typical Audio Amplifier Application Circuit with Single Ended Input

8W

Rf AUDIO INPUT

Pin Type Symbol Description

A1I INM Negative input of the first amplifier, receives the audio input signal. Connected to the

feedback resistor R f and to the input resistor R in.

A2O OUTA Negative output of the NCP2990. Connected to the load and to the feedback resistor Rf.

A3I INP Positive input of the first amplifier, receives the common mode voltage.

B1I VM_P Power Analog Ground.

B2I VM Core Analog Ground.

B3I V p Positive analog supply of the cell. Range: 2.2 V−5.5 V.

C1I BYPASS Bypass capacitor pin which provides the common mode voltage (Vp/2).

C2O OUTB Positive output of the NCP2990. Connected to the load.

C3I SHUTDOWN The device enters in shutdown mode when a low level is applied on this pin.

MAXIMUM RATINGS(Note 1)

Rating Symbol Value Unit Supply Voltage V p 6.0V Operating Supply Voltage Op Vp 2.2 to 5.5 V

2.0 V = Functional Only

−Input Voltage V in−0.3 to Vcc +0.3V Max Output Current Iout500mA Power Dissipation (Note 2)Pd Internally Limited−Operating Ambient T emperature T A−40 to +85°C Max Junction T emperature T J150°C Storage T emperature Range T stg−65 to +150°C Thermal Resistance Junction−to−Air R q JA(Note 3)°C/W

ESD Protection Human Body Model (HBM) (Note 4)

Machine Model (MM) (Note 5)−8000

>250

V

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

1.Maximum electrical ratings are defined as those values beyond which damage to the device may occur at T A = +25°C.

2.The thermal shutdown set to 160°C (typical) avoids irreversible damage on the device due to power dissipation.

3.The R q JA is highly dependent of the PCB Heatsink area. For example, R q JA can equal 195°C/W with 50 mm2 total area and also 135°C/W with

500 mm2. For further information see page 10. The bumps have the same thermal resistance and all need to be connected to optimize the power dissipation.

4.Human Body Model, 100 pF discharge through a 1.5 k W resistor following specification JESD22/A114.

5.Machine Model, 200 pF discharged through all pins following specification JESD22/A115.ELECTRICAL CHARACTERISTICS Limits apply for T A between −40°C to +85°C (Unless otherwise noted).

Characteristic Symbol Conditions

Min

(Note 6)Typ

Max

(Note 6)Unit

Supply Quiescent Current I dd V p = 2.6 V, No Load

V p = 5.0 V, No Load −

−

1.5

1.7

4mA

V p = 2.6 V, 8 W V p = 5.0 V, 8 W −

−

1.7

1.9

5.5

Common Mode Voltage V cm−−V p/2−V Shutdown Current I SD−0.020.3m A Shutdown Voltage High V SDIH− 1.2−−V Shutdown Voltage Low V SDIL−−−0.4V Turning On Time (Note 8)T WU C by = 1 m F−60−ms Turning Off Time T OFF−− 1.0−m s Output Impedance in Shutdown Mode Z SD−−10−k W

Output Swing V loadpeak V p = 2.6 V,R L = 8.0 W

V p = 5.0 V,R L = 8.0 W (Note 7)

T A = +25°C

T A = −40°C to +85°C

1.6

4.0

3.85

2.20

4.50

−

−

V

Rms Output Power P O V p = 2.6 V,R L = 4.0 W

THD + N < 0.1%

V p = 2.6 V,R L = 8.0 W

THD + N < 0.1%

V p = 5.0 V,R L = 8.0 W

THD + N < 0.1%−

−

0.40

0.30

1.20

−

−

W

Maximum Power Dissipation (Note 8)P Dmax V p = 5.0 V,R L = 8.0 W−−0.65W Output Offset Voltage V OS V p = 2.6 V

V p = 5.0 V

−3030mV

Signal−to−Noise Ratio SNR V p = 2.6 V, G = 2.0

10 Hz < F < 20 kHz

V p = 5.0 V, G = 10

10 Hz < F < 20 kHz −

−

84

77

−

−

dB

Positive Supply Rejection Ratio PSRR V+G = 2.0,R L = 8.0 W

Vp ripple_pp = 200 mV

C by = 1.0 m F

Input T erminated with 10 W

F = 217 Hz

V p = 4.2 V V p = 3.6 V V p = 3.0 V F = 1.0 kHz V p = 4.2 V V p = 3.6 V V p = 3.0 V −

−

−

−

−

−

−74

−72

−73

−80

−76

−77

−

−

−

−

−

−

dB

Efficiency h V p = 2.6 V,P orms = 320 mW

V p = 5.0 V,P orms = 1.0 W −

−

48

63

−

−

%

Thermal Shutdown T emperature (Note 9)T sd140160180°C

T otal Harmonic Distortion THD V p = 2.6,F = 1.0 kHz

R L = 4.0 W,A V = 2.0

P O = 0.32 W

V p = 5.0 V,F = 1.0 kHz

R L = 8.0 W,A V = 2.0

P O = 1.0 W −

−

−

−

−

−

−

0.04

−

−

0.02

−

−

−

−

−

−

−

%

6.Min/Max limits are guaranteed by design, test or statistical analysis.

7.This parameter is guaranteed but not tested in production in case of a 5.0 V power supply.

8.See page 9 for a theoretical approach of this parameter.

9.For this parameter, the Min/Max values are given for information.

Figure 2. THD+N versus Output Power

P OUT (mW)

T H D + N

(%)

Figure 3. THD+N versus Output Power

0.01

0.1

110

0100200300400500

P OUT (mW)

T H D + N (%)

Figure 4. THD+N versus Output Power

0.11

10

100200300400500600700800

P OUT (mW)

T H D + N

(%)

0.01

0.1

1

10

Figure 5. THD+N versus Output Power

T H D + N (%)

P OUT (mW)

Figure 6. THD+N versus Output Power

P OUT (mW)

T H D + N (%)

0.01

0.1

1

10

P OUT (mW)

T H D + N (%)

Figure 7. THD+N versus Output Power

20040060080010001200140016002.5

3 3.5

4 4.55Figure 8. Output Power versus Power Supply POWER SUPPLY (V)

O U T P U T P O W E R (m W )

Figure 9. THD+N versus Frequency

0.01

0.1

1

1001000

10000

FREQUENCY (Hz)

T H D +N (%)

Figure 10. THD+N versus Frequency 0.01

0.11

100

1000

10000

FREQUENCY (Hz)

T H D +N (%)

0.01

0.1

1

100

100010000

Figure 11. THD+N versus Frequency

FREQUENCY (Hz)

T H D +N (%)

10

100100010000

FREQUENCY (Hz)Figure 12. P SRR versus Frequency and

C BYP @ V P = 3.6 V, A V = 2P S S R (d B )

−70

−60

−50

−40−30−20

10

100

1 00010000

FREQUENCY (Hz)

P S S R (d B )

Figure 13. P SRR versus Frequency and C BYP

@ V P = 3.6 V, A V = 10

Figure 14. P SRR versus Frequency and

Gain @ V P = 3.0 V −80

−70

−60−50−40

10

100

1000

10000

FREQUENCY (Hz)P S S R (d B )

10

100

1000

10000

FREQUENCY (Hz)

P S S R (d B )

Figure 15. P SRR versus Frequency and

Gain @ V P = 3.6 V

−90−80−70−60−50−40−30−20P S S R (d B )

FREQUENCY (Hz)Figure 16. P SRR versus Frequency and

Gain @ V P = 4.2 V

010

20304050607080−40

−20

20

40

60

80

100

Figure 17. Turn On Time versus Room Temperature @ V BAT = 3.6 V,

C BYP = 1 m F, C IN = 100 nF, R IN = 22 k, R F = 110 k

T O N (m s )

ROOM TEMPERATURE (°C)

Figure 18. Turn On Time versus C BYP @ V BAT = 3.6 V, T A = +255C,

C IN = 100 nF, R IN = 22 k, R F = 110 k

2040608010012000.51 1.52 2.5

T O N (m s )

C BYP (m F)

Figure 21. Power Dissipation versus Output

Power

0.250

0.05P D , P O W E R D I S S

I P A T I O N (W )

P out , OUTPUT POWER (W)0.1

0.150.2

0.700.1P D , P O W E R D I S S I P A T I O N (W )

0.50.20.30.4

0.6Figure 22. Power Dissipation versus Output

Power

P out , OUTPUT POWER (W)

Figure 23. Power Derating − 9−Pin Flip−Chip CSP

7000P D , P O W E R D I S S I P A T I O N (m W )T A , AMBIENT TEMPERATURE (°C)

100200300400500600Figure 24. Maximum Die Temperature versus

PCB Heatsink Area

18040

60D I E T E M P E R A T U R E (°C ) @A M B I E N T T E M P E R A T U R E 25°C

PCB HEATSINK AREA (mm 2)

12080100160140

Detailed Description

The NCP2990 audio amplifier can operate under 2.6 V until 5.5 V power supply. With less than 1% THD + N, it can deliver up to 1.2 W RMS output power to an 8.0 W load (V P = 5.0 V). If application allows to reach 10% THD + N, then 1.6 W can be provided using a 5.0 V power supply. The structure of the NCP2990 is basically composed of two identical internal power amplifiers; the first one is externally configurable with gain−setting resistors R in and R f(the closed−loop gain is fixed by the ratios of these resistors) and the second is internally fixed in an inverting unity−gain configuration by two resistors of 20 k W. So the load is driven differentially through OUTA and OUTB outputs. This configuration eliminates the need for an output coupling capacitor.

Internal Power Amplifier

The output PMOS and NMOS transistors of the amplifier were designed to deliver the output power of the specifications without clipping. The channel resistance (R on) of the NMOS and PMOS transistors does not exceed 0.6 W when they drive current.

The structure of the internal power amplifier is composed of three symmetrical gain stages, first and medium gain stages are transconductance gain stages to obtain maximum bandwidth and DC gain.

Turn−On and Turn−Off Transitions

A cycle with a turn−on and turn−off transition is illustrated with plots that show both single ended signals on the previous page.

In order to eliminate “pop and click” noises during transitions, output power in the load must be slowly established or cut. When logic high is applied to the shutdown pin, the bypass voltage begins to rise exponentially and once the output DC level is around the common mode voltage, the gain is established instantaneously. This way to turn−on the device is optimized in terms of rejection of “pop and click” noises. The device has the same behavior when it is turned−off by a logic low on the shutdown pin. During the shutdown mode, amplifier outputs are connected to the ground using a 10 k W pulldown resistor.

When a shutdown low level is applied, with 1 m F bypass capacitor, it takes 65 ms before the DC output level is tied to Ground on each output. However, no audio signal will be provided to the BTL load instantaneously after the falling edge on the shutdown pin.

With 1 m F bypass capacitor, turn on time is set to 60 ms. Refer to Figures 17 and 18 for a complete study of this parameter. This fast turn on time added to a very low shutdown current saves battery life and brings flexibility when designing the audio section of the final application. NCP2990 is a zero pop noise device when using a single−ended audio input.

Shutdown Function

The device enters shutdown mode when shutdown signal is low. During the shutdown mode, the DC quiescent current of the circuit does not exceed 100 nA. In this configuration, the output impedance is 10 k W on each output.

Current Limit Circuit

The maximum output power of the circuit (Porms = 1.0 W,V p= 5.0 V, R L = 8.0 W) requires a peak current in the load of 500 mA.

In order to limit the excessive power dissipation in the load when a short−circuit occurs, the current limit in the load is fixed to 800 mA. The current in the four output MOS transistors are real−time controlled, and when one current exceeds 800 mA, the gate voltage of the MOS transistor is clipped and no more current can be delivered.

Thermal Overload Protection

Internal amplifiers are switched off when the temperature exceeds 160°C, and will be switched on again only when the temperature decreases fewer than 140°C.

The NCP2990 is unity−gain stable and requires no external components besides gain−setting resistors, an input coupling capacitor and a proper bypassing capacitor in the typical application.

The first amplifier is externally configurable (R f and R in), while the second is fixed in an inverting unity gain configuration.

The differential−ended amplifier presents two major advantages:

−The possible output power is four times larger (the output swing is doubled) as compared to a single−ended amplifier under the same conditions.

−Output pins (OUTA and OUTB) are biased at the same potential V p/2, this eliminates the need for an output coupling capacitor required with a single−ended amplifier configuration.

The differential closed loop−gain of the amplifier is given by A vd+2*R f

R in

+V orms

V inrms

.

Output power delivered to the load is given by P orms+(Vopeak)

2

2*R L

(Vopeak is the peak differential output voltage).

When choosing gain configuration to obtain the desired output power, check that the amplifier is not current limited or clipped.

The maximum current which can be delivered to the load is 500 mA I opeak+

V opeak

R L

.

Gain−Setting Resistor Selection (R in and R f )

R in and R f set the closed−loop gain of the amplifier.In order to optimize device and system performance, the NCP2990 should be used in low gain configurations.The low gain configuration minimizes THD + noise values and maximizes the signal to noise ratio, and the amplifier can still be used without running into the bandwidth limitations.

A closed loop gain in the range from 2 to 5 is recommended to optimize overall system performance.An input resistor (R in ) value of 22 k W is realistic in most of applications, and doesn’t require the use of a too large capacitor C in .

Input Capacitor Selection (C in )

The input coupling capacitor blocks the DC voltage at the amplifier input terminal. This capacitor creates a

high−pass filter with R in , the cut−off frequency is given by

fc +

1in in

.

The size of the capacitor must be large enough to couple in low frequencies without severe attenuation.

An input capacitor value between 33 nF and 220 nF performs well in many applications (With R in = 22 K W ).

Bypass Capacitor Selection (Cby)

The bypass capacitor Cby provides half−supply filtering and determines how fast the NCP2990 turns on. With a single−ended audio input, the amplifier will be a zero pop noise device no matter the bypass capacitor.

Figure 25. Schematic of the NCP2990 Demonstration Board

AUDIO INPUT

J6

J8

TP1*

V p TP2*OUTA TP3*

OUTB

Figure 26. Demonstration Board for 9−Pin Flip−Chip CSP Device − Silkscreen Layers

Item Part Description Ref.

PCB

Footprint Manufacturer

Manufacturer Refer-

ence

1NCP2990 Audio Amplifier−−ON Semiconductor NCP2990 2SMD Resistor 20 K W R1, R20805Panasonic ERJ−6GEYJ203V 4SMD Resistor 150 K W R30805Panasonic ERJ−6GEYJ203V 5Ceramic Capacitor 47 nF 100 V X7R C10805TDK C2012X7R2A473K 6Ceramic Capacitor 1.0 m F 10 V X7R C3, C40805TDK C2012X7R1A105K 7Jumper Header Vertical Mount, 2 positions, 100 mils J2, J6, J18100 mils Tyco Electronics / AMP5−826629−0 8I/O Connector, 2 positions J1, J5200 mils Phoenix Contact1757242 9Jumper Connector J7400 mils Harwin D3082−B01 10Not Mounted C2, TP1,

TP2, TP3

−−−

ORDERING INFORMATION

Device Marking Package Shipping†

NCP2990FCT2G MBA9−Pin Flip−Chip CSP

(Pb−Free)

3000/T ape and Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

NOTE:The NCP2990AFCT2G version requires a lead−free solder paste and should not be used with a SnPb solder paste.

NCP2990

PACKAGE DIMENSIONS

9 PIN FLIP−CHIP CASE 499E−01

ISSUE A

NOTES:

1.DIMENSIONING AND TOLERANCING PER 0.05C 0.03C

A B BOTTOM VIEW

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION