electronics

Chap 5. Field-Effect Transistor

FET: the current is controlled by an electric field applied perpendicular to the semiconductor surface and to the direction of current. Metal-Oxide-Semiconductor (MOSFET) Metal-Semiconductor FET (MESFET)

1.1

Structure

* Two-Terminal MOS structure with S/D grounded

(1) apply a negative bias to the gate with respect to the substrate, ⇒ induce an E-field with direction ↑.

Negative charges will exist on top of the gate plate.

In Si substrate, the majority HOLEs will move toward SiO 2/Si interface due to E-field appliction. ⇒Holes accumulate near the SiO 2/Si interface, “Accumulation”

(2) Apply a positive bias to the gate wrs the Si substrate.

⇒ induce an E-field with direction ↓.

Positive charges will exist on top of the metal plate.

In Si substrate, the majority HOLEs will repel from SiO 2/Si interface and leave negatively charged ions. (depletion) ⇒As V GS ↑, E-field ↑, minority Electrons are attracted to SiO 2/Si interface, “Inversion”

Threshold Voltage (V TH ): defined as the applied gate voltage needed to create an inversion layer in which the charge density = the conc. of majority carriers in Si substrate. In other words, V TH is the gate voltage required to “turn on” the transistor.

E V G < 0

E

V G > 0

E

For nMOS, if V TH >0, enhancement mode; if V TH <0, depletion mode For pMOS, if V TH >0, depletion mode; if V TH >0, enhancement mode,

* Transistor Structure

For V GS > 0 inversion layer is formed underneath the SiO 2/Si interface ⇒ n- channel region is formed and Connects the n + source and n + drain. .

If V DS > 0, ⇒ a current can be generated between S and D. Since the carriers moving in the channel are electrons, the MOSFET is called nMOS.

Similary, for PMOS, the carriers moving in the channel are “Holes” ⇒ n-Si substrate, P + Source and Drain.

(a) if V DS << V GS -V TH ,

⇒ the channel layer is almost constant ⇒ I D ∝ V DS

(b) as

V DS

↑, the voltage drop across the oxide near the drain

↓

⇒ the inversion charge density near the drain

↓

⇒ the incremental conductance at the drain ↓ ⇒ the slope of I D versus V DS ↓

(c) As V DS ↑ to V DS (sat) = V GS -V TH

⇒the inversion charge density near the drain= 0 ⇒ the conductance at the drain =0

⇒ the slope of I D versus V DS =0 (saturation)

(a) if V DS > V DS (sat), the point of zero inversion charge moves toward Source

⇒electrons enter the channel at the source, travel through the channel toward the drain, and then are injected into the depletion region, where they are swept by the E-field to drain ⇒” Saturation”

z I-V Characteristics

If V GS < V TH , “CUT OFF”

IF V GS > V TH , “ON”,

For V DS < V DS(sa t), “Nonsaturation”,

(

)

[]

22DS DS TH GS n D V V V V k I −−= where L C W k ox n n 2μ==

For V DS > V DS(sat), “Saturation” []2

TH GS n D V V k I −=independent of V DS

Note: the geometry, (W , L , or d ox ) is a variable in the design of MOSFETs

*Ckt Symbols and Conventions nMOSFET:

enhancement mode : V TH >0, a channel can be formed when V GS > V TH >0

depletion mode : V TH <0, a channel exists even at V GS = 0, so a negative voltage must be

applied to th edepletion mode-nMOSFET to turn it off.

Large signal equivalent ckt .

enhanced mode

depletion mode

Body Effect

If V sub-source = 0, V TH is a constant. If V sub-source ≠ 0, V TH is dependent on V sub-sourc by

In reality, I D ≠ 0 as ⇒

Breakdown

“Punchthrough” occurs when the drain voltage is large enough for the depletion region around the drain extend completely to the source terminal ⇒ I D increase rapidly (Breakdown)

Table Summary of Important MOSFET equations

√ i D

Common Source Circuit

• A source resistor R S is usually used to stabilize the Q -point of MOSFET against variation in

transistor parameters: (L , W , C ox , V TH ).

V TH = 1 V ,

k n = 0.1 mA/V 2 V THP = -0.8 V , k p = 0.2 mA/V 2

10 k Ω V TH = 2 V ,

k n = 0.1 mA/V 2

An enhancement load (V TH > 0 for nMOS and V TH < 0 for pMOS)

If an enhancement load device is connected with a MOSFET driver, this circuit can be used as an amplifier or as an inverter.

• Depletion Load (V TH < 0 for nMOS and V TH > 0 for pMOS)

If an enhancement load is connected with G & D shorting ⇒V G = V D ⇒V GS = V DS ⇒ V DS > V GS – V TH = V DS(sat) ⇒ transistor must be in “saturation” if it is on. Solution: (iii) V I = 5 V ,

⇒ V GS D = 5 V , V DS D

(sat) = V GS D –V TH D = 5-1 = 4V .

(iii) If M D is in saturation ⇒ V DS D > V DS D (sat) = 4V

⇒ Possibility is “LOW” (ii) Assume in M D “Nonsaturation”, (M L is known in “Sat”)

Θ M D and M L are in series, ∴I D D = I D L . ⇒ I D D =k n D [2(V GS D – V TH D ) V DS D – V DS 2D ] = I D L

= k n L (V GS L – V TH L )2

Θ V GS D = V I = 5 V , V DS D = V O , V GS L = V DS L =V DD – V O = 5- V O (iii)

⇒ k n D [2(V I – V TH D ) V O – V O 2] = I D L

= k n L (V DD – V TH L )2

⇒ 3 V O 2 – 24V O + 8 = 0

⇒ V O = 7.65 V (→←, Θ V O must < 5 V ) or 0.349 V ⇒ V O = 0.349 V = V DS D < 4 V (Right assumption) ⇒ I D = 133 μA

(2) if V I = 1.5 V ,

⇒ V GS D = 5 V > V TH D , M D is ON and V DS D (sat) = V GS D - V TH D = 0.5V ∴M D is very possible in “Saturation”, while M L is known in “Sat” (3) ⇒ I D D = I D L .

⇒ I D D =k n D (V GS D - V TH D )2 = k n L (V GS L - V TH L )2

⇒ V O = 3. V = V DS D > 0.5 V = V DS D (sat), “Right assumption ” ⇒ I D = 12.5 μA

“1” V I = 5 V , ⇒ V O = 0.349 V “0” “0” V I = 1.5 V , ⇒ V O = 3. V “1”

V GS = 0 > V TH , Θ V TH < 0 ∴ transistor M L is always “ON”

Solution: (1) V I = 5 V ,

⇒ V GS D = 5 V , V DS D (sat) = V GS D –V TH D = 5-1 = 4V .

(i) Assume in M D “Nonsaturation” and M L is in “Sat”

Θ M D and M L are in series, ∴I D D = I D L . ⇒ 5 V O 2 - 40V O + 4 = 0 ⇒ V O = 7.9 V (→←, Θ V O must < 5 V ) or 0.1 V

⇒ V O = 0.1 V = V DS D < 4 V = V DS D (sat) (Right

• Constant-current source Biasing

•

• Digital Logic Gate: (1) NMOS Inverter

Power Dissipation

Consider the power dissipation in a MOSFET inverter with V DD = 5 V , R D = 10 Ω, V TH = 0.8 V , k n =0.3 A/V 2.

If V I < V T H =0.8 V , ⇒ I D = 0, V O = V DD = 5V . ⇒ Power dissipated in the transistor is “zero”. If V I = V T H =0.8 V , assume M1 is in “Nonsaturation” ⇒ V O = V DD – k n R D [2(V I – V TH )V O – V O 2] ⇒ 3 V O 2 –26.2 V O + 5 = 0

⇒ V O = 0.195 or 8.54 (→←, Θ V O must be less than V DD )

⇒ I D = (V DD - V O )/R D = 0.48 A

(8) If V I < V TH , ⇒ M 1 is “OFF” ⇒ I D = 0, V O = V DD . (9) If V I > V TH , ⇒ M 1 is “ON” ⇒ V O = V DD - I D R D

As V I ↑, I D ↑ ⇒ V O ↓ (3)∴ V I “0” ⇒ V O “1”

V I “1” ⇒ V O “0” ⇒ “Inverter”

∴the power dissipated in the MOSFET is P T = I D • V DS = 0.48 x 0.195 = 93.6 mW ∴the power delivered to R D is

P R D = I 2D • R D = 2.34 mW

Digital Logic Gate

Amplifer

Consider an NMOS,

To get a linear amplification (V o /V i : linear), the MSOFET should be biased in saturation mode.

v GS = V GSQ (dc component) + v i (ac component)

⇒ i D = k n (V GS – V TH )2 = k n (V GSQ + v i – V TH )2 = k n [(V GSQ – V TH ) + v gs ]2 ⇒ i D = k n (V GSQ – V TH )2+ 2k n (V GSQ – V TH )v i + k n v i 2

Generally, v i << 2(V GSQ – V TH ) ∴v i 2 is much smaller and could be neglected ⇒ i D = k n (V GSQ – V TH )2+ 2k n (V GSQ – V TH )v i

⇒ The small-signal drain current transconductance g m :

I DQ i d =2k n (V GSQ –V TH )v gs ≡g m v gs V 1 V 2 V O 0V 0V “1” 5V 0V “0” 0V 5V “0” 5V

5V

“0”

⇑

↓⇒↑∴∝=−=∂∂≡m n DQ n TH GS n gs

d

m g L W L W k I k V V k v i g ,)

/(2)(2 Note:

1. With the Q point in the saturation region, the transistor operates as a constant current

source that is linearly controlled by v gs .

2. The g m of MOSFETs tends to be small compared to that of BJTs. However, the advantages of MOSFETs are:

(A) high input impedance

(B) Small size (high packing density) (C) Low power consumption

AC equivalent circuit of Common-Source amplifier

Example:

If R 1 and R 2 are biased the MOSFET in saturation mode, and the signal frequency is large enough for C C acts as a short circuit, the ac equivalent circuit becomes:

v o = -g m v gs (r o // R D ) v gs = v i

⇒ A v = v o /v i = -g m (r o //R D ) R i ≡ v i /i i = R 1//R 2

R o = v o /i o |v i = 0 = r o //R D

Source-Follower Amplifier

(Output is taken from the source terminal)

(1) v o = g m v gs (R S //r o ),

v i = v gs + v o = v gs [1+g m (R S //r o )] ⇒ 1)

//(1)

//(<+=

=o S m o S m i o V r R g r R g v v A (2) R in = R 1//R 2

(3) R o = v o /i o |v i = 0 ⇒ v g = 0, ∴v gs = -v S = -v o (4) o S m o S m o S o o o o m o iS o gs m o iS o o r R g r R g r R i v R v g r R v v g r R v i ////1)

//(1)

//()//()//(=+=≡⇒+=−=

Note: although the voltage gain A v of a source follower < 1, but its output resistance R o is very small compared to that of a common-source circuit. A small R o is desired when the circuit is to act as an ideal voltage source a drive a load circuit without suffering loading effects. ⎯ similar to Emitter-follower

Common-Gate configuration (Input: source, gate: grounded)

z R G is used to prevent the buildup of static charge on the gate. (1) v o = g m v gs (R D // R L ), v gs = -v i , ⇒ )//(L D m i

o

V R R g v v A == (2) ()L

D D

i o i gs m

i L

D D

gs

m O R R R I I A V

g I R R R V g I +=

=

⇒−=+−=

, (3) D V x x o m gs m gs i i in R I V R g V g V I V R i

===−−==

=0

,1

Summary of Three Basic Amplifier Configurations

Configuration V oltage gain Current gain R in R o Common-Source A V > 1 ⎯ ∞ Source-Follower A V ≤ 1 ⎯ ∞

Low

Common-Gate A V > 1

A i ~ 1

Low (1/g m )

CMOS Common-Source Amplifier

Small-Signal Equivalent Circuit:

V A o A o REF n

m A I V r I V r I L W k g , ,22211'

1

===

⎟⎠⎞

⎜⎝⎛=

Source Follower

()tn DD n

n V V L W k −⎟⎠⎞⎜⎝⎛=

→'1

(2) v I = 0 “Low”, ()tP DD P

P

v

SDP DSP SDP V V L W k i v r DD

V SDP +⎟⎠⎞

⎜⎝⎛=

∂∂=

→'1

The Voltage Transfer Characteristic (VTC)

For Q N , ()()n

n

n tN I o TN I n

n DN tN I o o o TN I n n DN k L W k where v v v for

v v L W k i v v v for v v v v L W k i =⎟⎠⎞⎜⎝⎛−≥−⎟⎠⎞⎜⎝⎛=−≤⎥⎦⎤⎢⎣

⎡−−⎟⎠⎞⎜⎝⎛='2

'2'212121 For Q P , ()()P

P

P tP I o TP I DD P

P DP tP I o o DD o

DD TP I DD P P DP k L W k where v v v for

v v V L W k i v v v for v V v V v v V L W k i =⎟⎠⎞⎜⎝⎛+≤−−⎟⎠⎞⎜⎝⎛=+≥⎥⎦

⎤⎢⎣⎡−−−−−⎟⎠⎞⎜⎝⎛='2

'2'21||||21||)(21)(|| The CMOS inverter is usually designed to have

(i) |V TN | = |V TP |

(ii) k n = k p (that is, k n ’(W/L)n = k p ’(W/L)p )⇒ p n

n

P L W L W μμ=⎟⎠⎞⎜⎝⎛⎟

⎠⎞⎜⎝⎛

+ SGP

+ GSN

Recall Chapter 1, V IL and V IH occur when 1−=∂∂I

o

v v , to determine V IH , we know that Q N is in “triode” region, Q P in “Saturation” region.

()()()()()()()()t DD t DD OL

IL L t DD t DD DD IH

OH H t DD IL P N IL t DD IH IH I DD IH O O IH I T I DD o o T I T DD TN DP DN V V V V V V NM V V V V V V V NM V V V Q Q V V V V V v V V v dt dv V v V v V v v V v V V V i i 23 023 23 25 :follows as determined be now can margins noise The 23

Nonsat."

" in is and Sat."" in is by determine can we Similarly,25get can we , ng Substituti 2 obtain

to 1 and substitute we whcih in 2121,1818

181

81 8

1

22+=−+=−=+=−−=−=+=⇒−==−

=−==−−=−−⇒−==Θ

Dynamic Operation

⎯ To determine the propagation delay of the inverter.

Assume a capacitor C (load) is connected between the output of the inverter and ground. Here C

represents the sum of the internal capacitors of next stages

Q N and Q

P .

Assume the circuit is symmetric (i.e., NMOS and PMOS are matched), ⇒ the rise time and fall time of the output waveform should be equal.

(1) C is charged through Q P from V DD (v I = 0, Q N is OFF)

(2) C is discharged through Q N to ground when v I is high, Q P is OFF.

P D = f CV DD2.

A figure of merit of a particular circuit technology is the “delay-power” product DP = P D•t P

It is observed that t P↑, P D↓, DP ~ constant.

An NMOS Analog Switch

A CMOS Transmission Gate As

As

+

v

_

MOSFET High-frequency Model

Homework 5.23, 5.38, 5.44, 5.76

As the Gate is “Closed”