Control and configuration software for a reconfigu

Reconfigurable Networking Hardware Platform

Todd S.Sproull,John W.Lockwood,David E.Taylor

Applied Research Laboratory

Washington University

Saint Louis,MO63130

Web:http://www.arl.wustl.edu/arl/projects/fpx/ Abstract—A suite of tools called NCHARGE(Networked Config-

urable Hardware Administrator for Reconfiguration and Govern-

ing via End-systems)has been developed to simplify the co-design

of hardware and software components that process packets within a

network of Field Programmable Gate Arrays(FPGAs).A key fea-

ture of NCHARGE is that it provides a high-performance packet in-

terface to hardware and standard Application Programming Inter-

face(API)between software and reprogrammable hardware mod-

ules.Using this API,multiple software processes can communicate

to one or more hardware modules using standard TCP/IP sockets. NCHARGE also provides a Web-Based User Interface to simplify the configuration and control of an entire network switch that con-tains several software and hardware modules.

I.I NTRODUCTION

An experimental platform called the Field Pro-grammable Port Extender(FPX)has been developed to enable the rapid deployment of hardware modules in net-works[1][2].In this system,data are processed by recon-figurable hardware,while control and configuration of the network system is implemented in software.Control cells are used to communicate between the hardware and soft-ware.

A suite of tools has been developed to manage the network of reconfigurable hardware on the FPX called NCHARGE(Networked Configurable Hardware Admin-istrator for Reconfiguration and Governing via End-systems).NCHARGE enables new hardware modules to be dynamically deployed onto the Field Programmable Gate Array(FPGA)logic of the FPX over a network. Once the hardware module is installed,NCHARGE con-trols the operation of each FPX by issuing customized control cells to control each hardware module. NCHARGE provides a standard Application Program-ming Interface(API)for software applications that com-municate with hardware.NCHARGE uses TCP/IP to communicate reliably with hosts on the Internet.It also implements a reliable protocol to transmit and receive messages between hardware and software,as shown in Figure1.Software applications,in turn,connect to NCHARGE via TCP/IP to issue commands to the remote hardware modules.One application that uses this ser-vice is an Internet routing module that forwards packets This research is supported by NSF:ANI-0096052and Xilinx Corp.End−system Web Interface

End−system Automated Software

Fig.1.Overview of system architecture:NCHARGE runs on the con-trol processor of a gigabit switch equipped with FPX reconfigurable hardware modules and communicates to end-systems via the Internet. in FPGA hardware and manages the data structures for a forwarding table in software.

NCHARGE also provides a web-based user interface so that remote users can perform remote operations on the FPX from distant end-systems.Through the web in-terface,users can reprogram the FPGAs on the FPX,up-date remote memory attached to the FPGAs,check the board’s status,or issue custom commands to their specific hardware module.In a fraction of a second,NCHARGE is able to program the FPX to act as an IP router from a web browser.With a few additional button clicks the router can be reconfigured.If the need arises,a new mod-ule can be loaded onto the FPX to perform,encryption, run length encoding,compression,and other customized packet processing functions.The features of NCHARGE fully exploit theflexibility of the reconfigurable hardware.

II.R EPROGRAMMABLE H ARDWARE P LATFORM

Reprogrammable hardware has proven to be effective at accelerating functions within a network[3][4].The ability to easily reprogram hardware via the Internet al-lows networking features to be deployed without physi-cal access to the hardware[5].The(FPX)is a network-ing hardware platform that has been built to perform dataprocessing for cells and packets in a high-speed network switch[6].

The FPX provides an open platform for the rapid proto-type and deployment of networking functions in hardware [7].Components of the FPX include two FPGAs,five banks of memory,and two high-speed network interfaces [2].Networking interfaces on the FPX were optimized to enable the simultaneous arrival and departure of data cells at SONET OC48rates.This is the equivalent bandwidth of multiple channels of Gigabit Ethernet.

The FPX integrates with another open hardware plat-form,the Washington University Gigabit Switch(WUGS) [8].By inserting FPX modules at each port of the switch, parallel FPX units can be used to simultaneously process packets on all ports of the network switch.

In a single rack mount cabinet,a system has been demonstrated that can hold8*2*2=32Xilinx Virtex FPGA devices connected via a20Gbps network switch. Hardware resources on the FPX have been designed in such a way as to promote ease of application develop-ment.Hardware modules use a standard interface to re-quest access to memory and execute memory transac-tions.The interfaces abstract application developers from device specific timing constraints,insulating hardware modules from changes in memory device technology. A.Network Interface Device(NID)

The FPX includes a statically-programmed FPGA that is called the Network Interface Device(NID).It controls how packetflows are routed to and from modules.The NID contains a per-flow switching module to selectively forward traffic between networking ports of the RAD,the switch,and an optical line card.The NID also provides mechanisms to dynamically load hardware modules over the network and into the router.The combination of these features allows data processing modules to be dynami-cally loaded and unloaded without affecting the process-ing of packets by the other modules in the system.

B.Reprogrammable Application Device(RAD)

The FPX also includes a dynamically-programmed FPGA that is called the Reprogrammable Application De-vice(RAD).The RAD enables application-specific func-tions to be implemented as dynamic hardware plug-in (DHP)modules[9].A DHP consists of a region of FPGA gates and internal memory,bounded by the well-defined interface.A standard interface has been implemented so that modules can transmit and receive packet data and communication with off-chip memories[10].

Each hardware module has a unique identification number(ModuleID)that is used for application-specific communication.When a control cell arrives at the input of a hardware module,it compares the ModuleIDfield in the control cell to the ModuleID stored within the mod-ule to determine if the control cell should be processed. If the control cell is addressed to the hardware module, the module processes the cell,builds a response cell,and sends the response cell back to NCHARGE.If the control cell is not addressed to the hardware module,the module simply passes the cell to its cell output interface,as the cell may be addressed to a subsequent module in the sys-tem or may be a response cell from a previous module in the system.

C.Control Cell Processor(CCP)

The Control Cell Processors(CCPs)are entities im-plemented in FPGA hardware on the NID and RAD that process control cells sent by NCHARGE.Control cells addressed to a CCP cause the hardware to perform an operation and generate a return message.Several types of control cells are used to perform the memory transac-tions.State machines within the CCPs read and write the physical memory at addresses specified in control cells. The CCPs perform memory transactions consisting of any combination of reads and writes to either of the SRAM devices or SDRAM devices[11].

In order to perform the reliable transmission protocol with the software,the CCP formats a response cell con-taining the data written to and read from the addresses in the designated memory device.The CCP also computes checksums to ensure the integrity of the messages.If a control cell is dropped or corrupted,another will be re-transmitted by NCHARGE to the CCP.

D.Reconfiguration Control(RC)

The Reconfiguration Control(RC)module prevents data and state loss when reconfiguring hardware modules in the RAD FPGA.In order to reconfigure a hardware module in the RAD FPGA,configuration data is sent to the NID where it is stored in an off-chip SRAM.When all configuration data has been received for the new mod-ule,the NID initiates a reconfiguration handshake with the RC in the RAD FPGA,designating the ModuleID of the module which is to be reconfigured.

III.S OFTWARE C OMPONENTS NCHARGE is the software component that controls re-programmable hardware on a switch.Figure2shows the role of NCHARGE in conjunction with multiple FPX de-vices within a switch.The software provides connectiv-ity between each FPX and multiple remote software pro-cesses via TCP sockets that listens on a well-defined port. Through this port,other software components are able to communicate to the FPX using its specified API.Because each FPX is controlled by an independent NCHARGE software process,distributed management of entire sys-tems can be performed by collecting data from multiple NCHARGE elements[12].

Fig.2.Detail of the hardware and software components that comprise the FPX system.Each FPX is controlled by an NCHARGE software process.The contents of the memories on the FPX modules can be modified by remote processes via the software API to NCHARGE. A.NCHARGE Features

NCHARGE provides an API for debugging,program-ming,and configuring an FPX.Specifically the API in-cludes commands to:check the status of an FPX,con-figure routing on the NID,perform memory updates, and perform full and partial reprogramming of the RAD. NCHARGE also provides a mechanism for applications to define their own custom control interface.

Control cells are transmitted by NCHARGE and pro-cessed by CCPs on the RAD or the NID.To update and configure routes for trafficflows,NCHARGE writes com-mands to modify routing entries on the gigabit switch or on the NID.To check the status of the FPX,NCHARGE sends a control cell to the NID or RAD and waits for a response.

To modify the content of memories attached to the FPX,NCHARGE supports several commands to perform memory updates.Applications can read or write words to the SRAM and SDRAM memory modules.These mem-ory updates are packed into control cells and sent to the FPX.The number of updates thatfit into a single control cell depends on the number of consecutive updates at a particular location in memory and the size of the mem-ory update.The size of the control word allows for up to eight32-bit address/data pairs to be specified in a single message.For full-width,36-bit memory words in SRAM, up to six words can be specified in a single control cell. For the-bit words in SDRAM,up to four words can

be updated at once.

Sending designs to an FPX via control cells is done by Fig. 3.Example of software applications communicating with NCHARGE

loading the NID memory with the design and then issuing another control cell for the NID to program the RAD.The content of memory can be a complete bitfile or a partial bitfile,as would be produced by a tool like PARBIT[13]. NCHARGE allows for a user to program a section of the RAD or the entire FPGA.

B.NCHARGE API

NCHARGE communicates with a wide range of soft-ware through the use of sockets.The API defines a set of text strings that comprise of NCHARGE commands. Once the command is sent to NCHARGE over its TCP socket the user will then receive a response control cell with any relevant return information as well as the indica-tion of a successful transmission.

C.Web Communication

All of the functionality of NCHARGE is brought to the web to allow a simple straight forward interface.The web interface also provides switch level configuration and maintenance.

A screen shot of the web page is shown in Figure4.Fig.4.Screen shot from the FPX Web Interface

This is the main page of the NCHARGE web interface. From here users select which commands to issue to an FPX.

The mechanism for handling the web-based commands is through the use of CGI scripts.Forms are processed by scripts,which in turn send commands to the NCHARGE software.The communication between NCHARGE and the web interface is done using a TCP socket program called‘basic send’.Basic send is discussed in more de-tail in the next section.

D.Cell Logging

NCHARGE can log control cells sent from and re-ceived by the control software.Logging can be en-abled,disabled through the web or command line inter-face.Futher,the contents of the logs can be viewed via the web.Each log is a textfile that contains the content of the cell and time the cell was transmitted.Figure5shows how logging can be enabled for cells transmitted to and from the NID and/or the RAD.

NCHARGE and the web interface look forfiles in a particular directory,for all references made to loading files or read fromfiles.A user may upload or editfiles over the network by using the web interface to access

the Fig.5.Screen shot from of the FPX Web Interface showing the cell logging functions

documents.The user has the ability to modify,upload or delete anyfile in NCHARGE public directory.

E.Socket API

NCHARGE monitors a well-known TCP port,then ac-cepts control connections via TCP/IP sockets.The soft-ware multiplexes control of the hardware among multi-ple software clients.One mechanism for issuing single commands is through a‘basic send’application.This program accepts control commands and returns the result via a remote control cell.These commands are the same as those that would be entered manually at a console or through a telnet session.Figure3illustrates how different applications can compose layered modules to communi-cate with NCHARGE through sockets.

F.VCI Updates and Status

NCHARGE allows user to issue a read status command to the NID to display the current state of the NID FPGA. Fields are set to display the current state of the FPX and a few special purposefields such as the RAD Programming byte count and the TYPE LINK.The RAD Programming Byte Count lists the number of bytes that the NID has programmed on the RAD.The TYPE LINK specifies the type of link connected to the FPX,which includes OC3, OC48,GLink,and Gigabit Ethernet.

G.Read and Write Memory

The SRAM and SDRAM memory on the RAD can be updated by issuing memory reads and writes.NCHARGE includes a web-based interface to issue these updates, which is shown in Figure6.The user specifies the type of memory operation(Read or Write)the memory width (32,36,orbits),the number of consecutive updates, (depends on the width,max of8for32bit,2for36bit, and4forbit values),the memory bank(0or1),the Module number(default is0for the SRAM and SDRAM) as well as a starting address.The32and36bit memory operations are for SRAM while thebit memory oper-ations are for SDRAM.By default,data is specified by the API in hex.Data can also be specified as strings of ASCII as shown in Figure6.A read string option is also available to let users read strings out of text.

The time required to reprogram the RAD over the net-work is governed by:(1)the time to send the bitfile over the network,(2)the time to transfer the configuration data into the FPGA.

H.Configuration Memory Updates

When programming the RAD with modules the user first must load the compiled FPGA bitfile onto the recon-figurable memory attached to the NID,as shown in Fig-ure7.Once it is loaded a separate command is issued to program the RAD,or a portion of the RAD.The Load RAD Memory command reads afile from the FPX switch controller and places it in the NID’s SRAM.Once loaded in the NID,a user may issue a partial or full reprogram

of Fig.6.Screen shot from of the FPX Web Interface showing memory updates and string updates

the RAD using the NID’s contents.When issuing the par-tial or full reprogram of the NID a user may also specify the offset in memory where the RAD to stored the bitfile. Loading a RAD design is done with the command Load RAD Memory radio button as shown in Figure8,where filename is the bitfile to send to the FPX.Partial and Full Programming are issued from the web page as well,here word offset is the location in the NID memory to start reading data from and byte count indicates the number of bytes that should be read to program the RAD.To per-form both the loading of a bitfile and the programming of the RAD,the Complete Configuration option was added. This allows a user to simply click here and load their hard-ware module.This performs the load command and the Full Programming command.

Using a Pentium III500MHz PC running NetBSD, benchmarks were performed to determine the actual time it takes to issue a Complete Configuration.For an 800KByte bitfile,a complete configuration takes4.5sec-onds.The limited rate of reconfiguration is caused by the use of the Stop and Wait protocol to issue program cells. By removing the Stop and Wait and launching cells at it as fast as possible that time drops to2.8seconds.Re-moving the CRC check brings the complete configuration time down to1.9seconds.

I.Batch Mode

NCHARGE can be used to issue a group of commands to be executed consecutively.The user specifies the com-mands in a textfile using the command line format and enters thefilename on the web page as shown in Figure9. NCHARGE then executes the sequence of commands by sending and receiving control cells to and from the NID.FPGA

NID

FPGA Memory

(3)NCHARGE Issues command to reconfigure

(4)NID Reads Memory and reprograms RAD FPGA

Interconnects

modules

FPX Fig.7.Diagram of control cells being sent from NCHARGE over a gigabit switch to program an FPX

Fig.8.Screen shot from of the FPX Web Interface that allows a user to

load NID configuration and program the RAD

Fig.9.Screen shot from of the FPX Web Interface that allows a user to issue a set of commands to the FPX Fig.10.Screen shot from of the FPX Web Interface showing the Create and Cells page

J.NCHRARGE Library calls

The NCHARGE tools include a C application program-ming interface library that allows communication with the FPX without explicit use of sockets.Functions defined in this API can be used to perform most types of FPX oper-ations.

K.Test Cell Generation

NCHARGE includes software to send and receive raw ATM cells to the FPX.This feature is handled through the web interface to allow a user to specify a payload and the type format.Cells maybe formatted as AAL0/AAL5 Frames,IP packets,or UDP datagrams.Cells are sent, NCHARGE waits for a response on a specified VCI and reports a timeout if no cells were returned to the switch controller.

Fig.11.Second Page after creating cells and waiting to send cells

ModID

OpCode HEC

HDR PL2PL3PL4PL5PL6PL7PL8PL9PL10PL11

PL1Fig.12.Layout of a software plug-in module inside a control cell

L.Extendable Modules

NCHARGE allows unique control cells to be defined for customized communication between hardware and software.These custom control cells give a user complete control over the payload (12words)of a cell.Figure 12shows a sample control cell that has been customized to communicate parameters for the Fast IP Lookup Module.M.Example:Fast IP Lookup Memory Manager The Fast Internet Protocol Lookup (FIPL)engine,de-veloped at Washington University in St.Louis,is a high-performance,solution to perform IP address lookups.It performs a longest prefix match over 32bit destination ad-

dresses.This module is used to implement Internet Rout-ing on the FPX.[14]

The Fast IP Lookup (FIPL)memory manager is a stand alone application that accepts commands to add,delete,and update routes.The program maintains a trie data structure in memory on the processor and then pushes up-dates to the SRAM on the FPX.

The Fast IP Lookup (FIPL)application is loaded as a module on the FPX.A few other software components in-terconnect the FIPL memory manager with remote hosts and the NCHARGE software.The first piece of soft-ware is ‘write fip’,this accepts FIPL memory manager commands on a specified TCP port from the httpd web server that processed the commands.It then forwards the commands to the FIPL memory manager.These com-mands are of the form ‘Add route A 1.A 2.A 3.A 4/netmask nexthop’,‘Delete Route A 1.A 2.A 3.A 4/netmask’.FIPL memory manager processes these route updates and out-puts memory update commands suited for NCHARGE.These memory updates are then piped to another applica-tion which reads in multiple memory updates and issues them to NCHARGE over a TCP socket.NCHARGE then packs the memory updates into as few cells as possible and sends them to the FPX attached to the switch.The overall flow of data with FIPL and NCHARGE is shown in Figure 13.

The format of control cells sent between hardware and software is broken down into fields,as shown in Fig-ure 14.These fields are defined in an XML style format.The first field is the module name.This is a simple string identifier that displays to the user which modules are cur-rently installed on NCHARGE.This field identifies the module name as well as version number.The second field enumerates the input opcodes.In the example shown,the user is specifying several different fields,called the ‘Root Node Pointer‘,‘IP Flows 1and 2’,as well as the ‘Control Cell VCI’.

Inside the input opcodes field,the first line declares the Root Node Pointer variable.This variable will be used as a parameter for opcode 0x10.The next XML field de-fines the output opcodes.These fields define the return cells sent from FPX as decoded by NCHARGE.The out-put code lists the opcode,the number of variables to read,the output syntax,as well as the specified variables.Here the Root Node Pointer has one variable to read for its re-sponse.

The next XML field is the fields section.This area de-clares all variables used by the custom control software as well as its location in the control cell.The parameters here are the variable name,start word in the data,most significant bit of the control cell,stop word in the data,and the least significant bit.

The final field is the help section.This is a string field that gives the user the keyboard arguments associ-

FIPL Memory Manager

Remote Host

FPX Control Processor

Fig.13.Example of dataflow from Web Interface to FPX

ated with each command.This is useful for the command

line mode of the control software to provide a summary of

the plug-in modules features.Thisfield is not necessary

in a web implementation of a module.

To use the customized control cells,a module isfirst

loaded into NCHARGE.From the web page,the module

to load is selected as well as the ID used to reference the

module.After loading the module the probe command

can be issued to verify the module was loaded and list

other models loaded into NCHARGE.To use a module,

commands can be issued from the generic model inter-

face on the web or through a custom web page for their

specific module.When a user wishes tofinish using the

module they may unload it by issuing the Unload Module

Command specifying the module id.

IV.P ERFORMANCE

For applications like FIPL,the rate at which memory

can be updated is a major factor in the overall perfor-

mance of the application.In order to gain insight into the

performance of NCHARGE,several experiments were

conducted to measure the memory throughput as a func-

tion of word width and number of updates packed into a

transaction.Figure15shows how the memory through-

put increases for larger numbers of updates for each of

the three types of memory operations supported on the

FPX(32-bit,36-bit,and-bit).The discontinuity of the

performance is due to the number of address/data mem-

ory update pairs thatfit into a single message.For32-bit

data operations,the number of updates is limited to eight.

Thus,when a transaction includes a9th memory update,

two messages must be transmitted from software to hard-

ware.Similar jumps are visible for the36-bit and-bit

updates,occurring at six and four updates per message,

respectively.

Figure16shows how the memory throughput of

NCHARGE is affected by the processor performance,the

error control protocol,and the application type.Two pro-

cessors were used to evaluate the performance:an AMD

Athlon running at1100MHz and an Intel Pentium Pro

running at200MHz,both machines communicated with

the WUGS via a Gigabit link interface card.The perfor-

mance was evaluated both with and without the use of the

Stop and Wait error control protocol.The Stop and Wait

protocol is not needed if the network connection between

hardware and software is error-free(i.e.,cells are never

dropped or corrupted).Lastly,the performance was mea-

sured for both local and remote applications.For local ap-

plications,a procedure to send control messages was run

directly on the local FPX control processor,while for re-

mote applications,all transactions were conducted though

an additional TCP/IP socket.

The best performance of200,000updates per second,

was obtained for local applications transmitting messages

without stop and wait on the fast processor.Disabling

the Stop and Wait protocol on the fast processor increases

performance significantly because the throughput is lim-

ited only by the rate at which the processor can issue com-

mands.The performance is degraded by approximately

25%for applications that use the TCP/IP socket interface.

The performance is degraded further when NCHARGE

runs over an unreliable link using the Stop and Wait pro-

tocol.For the slow processor,the performance does not

vary as much with the changes in protocols because the

software is limited by the performance of the processor.

V.R ELATED W ORK

There are other systems that perform reconfigurable

computing on FPGAs.SPLASH2[15]was an early im-

plementation of reconfigurable computing that led to the

commercial developement of the Wildforce,Wildstar,and

Wildfire[16]boards from AnnapolisMicro.The Wildstar

contains a Virtex FPGA and is attached to the PCI bus

of a host machine.The control of the Wildstart products

is via the Wild Application Programming Interface(Wild

API).The device also allows for‘Internet Reconfigura-

tion’.This is made possible through the use of the JBits

Interface software[17].

Some of the applications developed for the FPX have

been previously implemented on an FPGA.Specifically,

Fast IP Lookup Example Module 1.0

0x10,R,1,Root Node Pntr,0x12,I,1,IP Flow 1,0x14,F,1,IP Flow 2,

0x16,B,2,IP Flow 1,IP Flow 2,0x18,C,1,Control Cell VCI,

0x11,1,Root node pntr is,Root Node Pntr,0x13,1,IP Flow 1updated to ,IP Flow 1,0x15,1,IP Flow 2updated to ,IP Flow 2,

0x17,2,2IP Flows updated to ,IP Flow 1,IP Flow 2,0x19,1,New Control Cell VCI is ,Control Cell VCI,<fields >

Root Node Pntr,x,1,31,1,13,IP Flow 1,x,2,31,2,16,IP Flow 2,x,2,15,2,0,

Control Cell VCI,x,3,31,3,16,

R Root Node Pointer address update:R address (hex)I Update IP Flow 1:I address (hex)F Update IP Flow 2:F address (hex)

B Update IP Flows 1and 2:b address1address2(hex)

C Update Control Cell VCI:C VCI (hex)

Fig.14.Fast IP Lookup Software Plug-in Module

10000

20000

30000

40000

50000

60000

70000

80000

05

10152025

U p d a t e s p e r S e c o n d

Number of Updates

Write 32Write 36Write

Fig.15.Memory throughput as a function of 32-bit,36-bit,and -bit memory sizes and number of updates

50000

100000

150000

200000

250000

05

10152025

U p d a t e s p e r S e c o n d

Number of Updates

Fig.16.Memory throughput as a function of processor (AMD Athlon 1100vs.Pentium Pro 200),error control mechanism (Stop and Wait vs.none),and application type (local application vs.remote TCP socket)

circuits which provide IP routing have been implemented.The previous work,however,does not scale,update,or route as fast as FIPL [18].An API for reconfigurable computing has also been developed to control and com-municate with an arbitrary device.NCHARGE sets it-self apart from these solutions in that it has the ability to program an FPGA over the Internet,perform partial pro-gramming of an FPGA,and can deliver customized con-trol interfaces to software applications.

VI.C ONCLUSION

A suite of tools called NCHARGE has been developed to manage the reconfigurable hardware within an Internet router or firewall.NCHARGE provides an efficient mech-anism to monitor the status of remote hardware,configure network traffic flows,reprogram hardware,and perform updates to memory.The rate at which NCHARGE can update remote memory has been measured to be 200,000updates per second.NCHARGE is able to load a bitfile to the NID program memory in 1.8seconds.The time to program the RAD from the NID is 16milliseconds.A standard API has been defined in NCHARGE to commu-nicate between software applications and hardware mod-ules.NCHARGE supports an XML-like language to de-fine an API and control message format for customized hardware modules.This feature was used to implement the communication interface between the hardware and software components of the Fast IP Lookup (FIPL)al-gorithm.Lastly,a web-based interface has been imple-mented to provide an intuitive interface to the hardware of the Field Programmable Port Extender.

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