用VHDL实现分频器

use IEEE.STD_LOGIC_11.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fenpin is

     Port ( RESET : in std_logic;

CLK : in std_logic;

           CLKOUT1 : out std_logic

CLKOUT1 : out std_logic

CLKOUT1 : out std_logic);--分配三个输出口

end fenpin;

architecture Behavioral of fenpin is

signal div_val1: integer range 0 to 2;   --分频值＝2*2

signal div_val2: integer range 0 to 4;

signal div_val3: integer range 0 to 8;

    signal div_clk1 : std_logic;--因为CLKOUT是out类型，

                            --用div_clk1来暂存

    signal div_clk2 : std_logic;

signal div_clk3 : std_logic;

begin

process(CLK,RESET)

  begin

      if(RESET='0') then--RESET的优先级最高

       div_clk1 <= '0';

        div_clk2 <= '0';

        div_clk3 <= '0';

      elsif(CLK'event and CLK='1') then --判断CLK上升沿

         if(div_val1=2) then

           div_val1<= 0;

           div_clk1 <= not div_clk1;

        else

           div_val1 <= div_val1 + 1;--在CLK的上升

                  --沿div_val1自加1，加到2时清零并将div_clk1取反

                end if;

        if(div_val2=4) then

           div_val2 <= 0;

           div_clk2 <= not div_clk2;

        else

           div_val2 <= div_val2 + 1;--在CLK的上升

                  --沿div_val2自加1，加到4时清零并将div_clk2取反

                end if;

if(div_val3=8) then

           div_val3 <= 0;

           div_clk3 <= not div_clk3;

        else

           div_val3 <= div_val3 + 1;--在CLK的上升

                  --沿div_val3自加1，加到8时清零并将div_clk3取反

                end if;

           end if;    

 end process;

CLKOUT1 <= div_clk1;

CLKOUT2 <= div_clk2;

CLKOUT3 <= div_clk3;

 end Behavioral;