ths7316

FEATURES

DESCRIPTION

APPLICATIONS

DAC/Encoder

W

HDTV 720p/1080i VGA SVGA XGA

Y’P’P’G’B’R’B R W

W

THS7316

SLOS521A–MARCH 2007–REVISED JANUARY 2008

www.ti.com

3-Channel HDTV Video Amplifier With 5th -Order Filters and 6-dB Gain

•3HDTV Video Amplifiers for Y'P'B P'R 720p and 1080i,G'B'R'(R'G'B'),VGA/SVGA/XGA Fabricated using the Silicon-Germanium (SiGe)BiCom-III process,the THS7316is a low power •

Integrated Low-Pass Filters

single-supply 3-V to 5-V,3-channel integrated video –5th -Order 36-MHz (–3dB)Butterworth Filter buffer.It incorporates a 5th-order modified ––1dB Passband Bandwidth at 31MHz Butterworth filter which is useful as a DAC –30dB Attenuation at 74MHz reconstruction filter or an ADC anti-aliasing filter.The 36-MHz filter is a perfect choice for HDTV video •

Versatile Input Biasing

which includes Y'P'B P'R 720p/1080i,G'B'R'(R'G'B'),–DC-Coupled With 140-mV Input Shift and VGA/SVGA/XGA signals.

–AC-Coupled with Sync-Tip Clamp As part of the THS7316flexibility,the input can be –Allows AC-Coupled With Biasing configured for ac or dc coupled inputs.The DC +•Built-in 6-dB Gain (2V/V)

140-mV input offset shift to allow for a full sync dynamic range at the output with 0-V input.The AC •3-V to 5-V Single Supply Operation coupled modes include a transparent sync-tip clamp •

Rail-to-Rail Output:

option for signals with sync such as Y’or Green with –Output Swings Within 100mV From the sync.AC-coupled biasing for P’B /P’R /Non-sync channels can be achieved by adding an external Rails Allowing AC or DC Output Coupling resistor.

–Supports Driving 2Lines per Channel

The THS7316is the perfect choice for all output •Low 18.3-mA at 3.3-V Total Quiescent Current buffer applications.Its rail-to-rail output stage with •Low Differential Gain/Phase of 0.1%/0.1°6-dB gain allows for both ac and dc line driving.The •

SOIC-8Package

ability to drive 2video lines per channel,or 75-Ωloads,allows for maximum flexibility as a video line driver.The 18.3-mA total quiescent current makes it an excellent choice for USB powered,portable,or •Set Top Box Output Video Buffering other power sensitive video applications.

•PVR/DVDR Output Buffering

•

USB/Portable Low Power Video Buffering

The THS7316is available in a small SOIC-8package that is RoHS compliant.

Figure 1.3.3-V Single-Supply DC-Input/DC Output Coupled Video Line Driver

Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.Copyright ©2007–2008,Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas Instruments standard warranty.Production processing does not necessarily include testing of all parameters.

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ABSOLUTE MAXIMUM RATINGS

DISSIPATION RATINGS

RECOMMENDED OPERATING CONDITIONS

THS7316

SLOS521A–MARCH 2007–REVISED JANUARY 2008

This integrated circuit can be damaged by ESD.Texas Instruments recommends that all integrated circuits be handled with appropriate precautions.Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure.Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGING/ORDERING INFORMATION

PACKAGED DEVICES

PACKAGE TYPE (1)

TRANSPORT MEDIA,QUANTITY

THS7316D Rails,75SOIC-8

THS7316DR

Tape and Reel,2500

(1)

For the most current package and ordering information,see the Package Option Addendum at the end of this document,or see the TI Web site at www.ti.com .

over operating free-air temperature range (unless otherwise noted)

(1)

VALUE UNIT Supply voltage,V S+to GND

5.5V V I Input voltage –0.4V to V S+

V I O Output current

±90mA Continuous power dissipation

See Dissipation Rating Table

T J Maximum junction temperature,any condition (2)

150°C T J Maximum junction temperature,continuous operation,long term reliability (3)125°C T stg

Storage temperature range

–65to 150°C HBM

2000ESD ratings

CDM 1500V

MM

200

(1)Stresses above those listed under absolute maximum ratings may cause permanent damage to the device.These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute maximum rated conditions for extended periods may degrade device reliability.(2)The absolute maximum junction temperature under any condition is limited by the constraints of the silicon process.

(3)

The absolute maximum junction temperature for continuous operation is limited by the package constraints.Operation above this temperature may result in reduced reliability and/or lifetime of the device.

POWER RATING (1)

θJC θJA (T J =125°C)

PACKAGE (°C/W)(°C/W)T A =25°C T A =85°C SOIC-8(D)

16.8

130(2)

769mW

308mW

(1)Power rating is determined with a junction temperature of 125°C.This is the point where performance starts to degrade and long-term reliability starts to be reduced.Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and reliability.

(2)

This data was taken with the JEDEC High-K test PCB.For the JEDEC low-K test PCB,the θJA is 196°C/W.

MIN

MAX

UNIT V S+Supply voltage 35V T A

Ambient temperature

–40

85

°C

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Channel 3

Output

Channel 1

Output

Channel 2

Output

Channel 3

Input

Input

Channel 2

Input

PIN CONFIGURATION

CH.1 IN

CH.2 IN

CH.3 IN

V

S+

CH.1 OUT

CH.2 OUT

CH.3 OUT

GND

THS7316

THS7316

SLOS521A–MARCH2007–REVISED JANUARY2008

FUNCTIONAL DIAGRAM

SOIC-8(D)

(TOP VIEW)

TERMINAL FUNCTIONS

TERMINAL

I/O DESCRIPTION

NAME NO.SOIC-8

CH.1–INPUT1I Video Input–Channel1

CH.2–INPUT2I Video Input–Channel2

CH.3–INPUT3I Video Input–Channel3

+Vs4I Positive Power Supply Pin–connect to3V to5V.

GND5I Ground Pin for all internal circuitry.

CH.3–OUTPUT6O Video Output–Channel3

CH.2–OUTPUT7O Video Output–Channel2

CH.1–OUTPUT8O Video Output–Channel1

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ELECTRICAL CHARACTERISTICS V S+=3.3V:

THS7316

SLOS521A–MARCH 2007–REVISED JANUARY 2008

R L =150Ωto GND –Reference Figure 2and Figure 3(unless otherwise noted)

TYP

OVER TEMPERATURE 0°C to –40°C to MIN/PARAMETER

TEST CONDITIONS

25°C

25°C

70°C

85°C

UNITS

MAX/TYP AC PERFORMANCE

Small-signal bandwidth (–3dB)V O –0.2V PP (1)

3631/4330/4430/44MHz Min/Max Large-signal bandwidth (–3dB)V O –2V PP

(1)

3631/4330/4430/44MHz Min/Max –1dB Passband bandwidth 31MHz Typ Attenuation

f =27MHz (2)0.3–0.3/2.4–0.35/2.4

–0.4/2.6dB Min/Max With respect to 100kHz f =74MHz (2)3020

19

19

dB Min Group delay

f =100kHz 16.2ns Typ Group delay variation f =27MHz 5.4ns Typ with respect to 100kHz Channel-to-channel delay 0.3ns

Typ Differential gain NTSC /PAL 0.1/Typ

0.15%Differential phase NTSC /PAL

0.1/0.1°Typ Total harmonic distortion f =1MHz;V O =2V PP

–70dB Typ Signal to noise ratio

No Weighting,100kHz to 37.5MHz 67dB Typ Channel-to-channel crosstalk f =1MHz –61dB

Typ AC Gain –All channels 6 5.7/6.3

5.65/

6.35

5.65/

6.35

dB Min/Max Output Impedance f =10MHz 0.5

Ω

Typ DC PERFORMANCE Biased output voltage V I =0V

285210/370

200/380

190/390

mV Min/Max Input voltage range

DC input,limited by output –0.1/1.46V Typ Sync tip clamp charge current V I =–0.1V

360µA Typ Input resistance 800k ΩTyp Input capacitance

2

pF Typ OUTPUT CHARACTERISTICS

R L =150Ωto 1.65V

3.15V

Typ R L =150Ωto GND 3.1 2.85

2.75

2.75

V Min High output voltage swing

R L =75Ωto 1.65V 3.1V Typ R L =75Ωto GND

3.0V Typ R L =150Ωto 1.65V (V I =–0.15V)

0.14V

Typ R L =150Ωto GND (V I =–0.15V)0.080.17

0.2

0.21

V Max Low output voltage swing

R L =75Ωto 1.65V (V I =–0.15V)0.3V Typ R L =75Ωto GND (V I =–0.15V)

0.1V Typ Output current (sourcing)R L =10Ωto 1.65V 80mA Typ Output current (sinking)R L =10Ωto 1.65V

70

mA

Typ POWER SUPPLY

Maximum operating voltage 3.3 5.5 5.5 5.5V Max Minimum operating voltage 3.3 2.85 2.85 2.85V Min Maximum quiescent current V I =0V 18.322.52323.4mA Max Minimum quiescent current V I =0V

18.314

13.6

13.1

mA Min Power Supply Rejection (+PSRR)

52

dB

Typ

(1)The Min/Max values listed for this specification are specified by design and characterization only.

(2) 3.3-V Supply Filter specifications are specified by 100%testing at 5-V supply along with design and characterization only.

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ELECTRICAL CHARACTERISTICS V S+=5V:

THS7316 SLOS521A–MARCH2007–REVISED JANUARY2008

R L=150Ωto GND–Reference Figure2and Figure3(unless otherwise noted)

TYP OVER TEMPERATURE

0°C to–40°C to MIN/ PARAMETER TEST CONDITIONS

25°C25°C70°C85°C UNITS MAX/

TYP

AC PERFORMANCE

Small-signal bandwidth(–3dB)V O–0.2V PP(1)3631/4330/4430/44MHz Min/Max Large-signal bandwidth(–3dB)V O–2V PP(1)3631/4330/4430/44MHz Min/Max –1dB Passband bandwidth31MHz Typ Attenuation f=27MHz0.3–0.3/2.4–0.35/2.5–0.4/2.6dB Min/Max With respect to100kHz f=74MHz30201919dB Min Group delay f=100kHz16.1ns Typ

Group delay variation

f=27MHz 5.4ns Typ with respect to100kHz

Channel-to-channel delay0.3ns Typ Differential gain NTSC/PAL0.1/Typ

0.15%

Differential phase NTSC/PAL0.1/0.1°Typ Total harmonic distortion f=1MHz;V O=2V PP–70dB Typ Signal to noise ratio No Weighting,100kHz to37.5MHz67dB Typ Channel-to-channel crosstalk f=1MHz–62dB Typ

AC Gain–All channels6 5.7/6.3 5.65/6.35 5.65/6.35dB Min/Max Output Impedance f=10MHz0.5ΩTyp

DC PERFORMANCE

Biased output voltage V I=0V290210/370200/380190/390mV Min/Max Input voltage range Limited by output–0.1/2.3V Typ Sync tip clamp charge current V I=–0.1V380µA Typ Input resistance800kΩTyp Input capacitance2pF Typ OUTPUT CHARACTERISTICS

R L=150Ωto2.5V 4.85V Typ

R L=150Ωto GND 4.7 4.2 4.1 4.1V Min High output voltage swing

R L=75Ωto2.5V 4.7V Typ

R L=75Ωto GND 4.5V Typ

R L=150Ωto2.5V(V I=–0.15V)0.19V Typ

R L=150Ωto GND(V I=–0.15V)0.090.230.260.27V Max Low output voltage swing

R L=75Ωto2.5V(V I=–0.15V)0.35V Typ

R L=75Ωto GND(V I=–0.15V)0.1V Typ Output current(sourcing)R L=10Ωto2.5V90mA Typ Output current(sinking)R L=10Ωto2.5V85mA Typ POWER SUPPLY

Maximum operating voltage5 5.5 5.5 5.5V Max Minimum operating voltage5 2.85 2.85 2.85V Min Maximum quiescent current V I=0V19.3232526mA Max Minimum quiescent current V I=0V19.314.714.213.8mA Min Power Supply Rejection(+PSRR)52dB Typ (1)The Min/Max values listed for this specification are specified by design and characterization only.

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R

LOAD LOAD LOAD

V SOURCE

R

V SOURCE

LOAD

LOAD

LOAD

THS7316

SLOS521A–MARCH2007–REVISED JANUARY2008

Figure2.DC Coupled Input and Output Test Circuit

Figure3.AC Coupled Input and Output Test Circuit

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TYPICAL CHARACTERISTICS

f −Frequency −MHz

−60

−50−40−30−20−100

10S m a l l -S i g n a l G a i n −d B

0.1

10

100

1k

1

−360

−315−270−225−180−135−90−45

045f −Frequency −MHz

P h a s e −o

0.1

10

100

1

2.5

3.03.5

4.04.5

5.05.5

6.0

6.5f −Frequency −MHz

S m a l l -S i g n a l G a i n −d B

1

100

10

f −Frequency −MHz

20

G r o u p D e l a y −n s

0.1

10

100

1

25

1015

f −Frequency −MHz

−60

−50−40−30−20−10010S i g n a l G a i n −d B

10

100

1k

1

f −Frequency −MHz

−60

−50−40−30−20−10010S m a l l -S i g n a l G a i n −d B

10

100

1k

1

SMALL-SIGNAL GAIN vs FREQUENCY

PHASE vs FREQUENCY

Figure 4.

Figure 5.

SMALL-SIGNAL GAIN vs FREQUENCY

GROUP DELAY vs FREQUENCY

Figure 6.

Figure 7.

SMALL-SIGNAL FREQUENCY RESPONSE vs

LARGE-SIGNAL FREQUENCY RESPONSE

CAPACITIVE LOADING

Figure 8.Figure 9.

V −Output Voltage −V O PP

-90-70-60-40-30-202n d O r d e r H a r m o n i c D i s t o r t i o n −d B

2.5

3

0.5

1

1.5

2

-80

-50

V −Output Voltage −V O PP

-90-70-60-40-30-20

3r d O r d e r H a r m o n i c D i s t o r t i o n −d B

0.5

1.5

1

2

2.5

3

-80-50

-100

f −Frequency −MHz

−90

−80−70−60−30S m a l l -S i g n a l G a i

n −d B

0.1

10

1001k

1−50−40f −Frequency −MHz

−60

−50−40−30−20−100

10S m a l l -S i g n a l G a i n −d B

0.1

10

100

1k

1

−360

−315−270−225−180−135−90

−450

45f −Frequency −MHz

P h a s e −o

0.1

10

100

1

2.5

3.03.5

4.04.5

5.05.5

6.0

6.5f −Frequency −MHz

S m a l l -S i g n a l G a i n −d B

1

100

10

SLOS521A–MARCH 2007–REVISED JANUARY 2008

TYPICAL CHARACTERISTICS (continued)

2nd HARMONIC DISTORTION vs

3rd HARMONIC DISTORTION vs

OUTPUT VOLTAGE

OUTPUT VOLTAGE

Figure 10.

Figure 11.

CROSSTALK vs FREQUENCY

SMALL-SIGNAL GAIN vs FREQUENCY

Figure 12.

Figure 13.

PHASE vs FREQUENCY

SMALL-SIGNAL GAIN vs FREQUENCY

Figure 14.Figure 15.

f −Frequency −MHz

20

G r o u p D e l a y −n s

0.1

10

100

1

25

1015

f −Frequency −MHz

−60

−50−40−30−20−100

10S i g n a l G a i n −d B

10

100

1k

1

f −Frequency −MHz

−60

−50−40−30−20−100

10

S m a l l -S i g n a l G a i n −d B

10

100

1k

1

V −Output Voltage −V O PP

-90-70-60-40-30-202n d O r d e r H a r m o n i c D i s t o r t i o n −d B

3.5

4.5

0.5

1.5

1

2

2.5

3

4

-80

-50

f −Frequency −MHz

−90

−80

−70−60−30

S m a l l -S i g n a l G a i n −d B

0.1

10

1001k

1−50−40V −Output Voltage −V O PP

-90-70-60-40-30-20

3r d O r d e r H a r m o n i c D i s t o r t i o n −d B

3.5

4.5

0.5

1.512

2.534-80-50-100

TYPICAL CHARACTERISTICS (continued)

GROUP DELAY vs FREQUENCY

LARGE-SIGNAL FREQUENCY RESPONSE

Figure 16.

Figure 17.

SMALL-SIGNAL FREQUENCY RESPONSE vs

2nd HARMONIC DISTORTION vs

CAPACITIVE LOADING

OUTPUT VOLTAGE

Figure 18.

Figure 19.

3rd HARMONIC DISTORTION vs

OUTPUT VOLTAGE

CROSSTALK vs FREQUENCY

Figure 20.Figure 21.

T −Ambient Temperature −C A o 17.5

18

18.5

19

19.5

20I Q u i e s c e n t C u r r e n t −m A

Q −0

6090

-30-40-10-2010203040507080

T −Ambient Temperature −C

A o 5.9

5.92

5.96

6.046.08

A −d B

V −V o l t a g e G a i n 0

6090

-30-40-10-20102030405070806.0666.025.985.94T −Ambient Temperature −C A o 0

0.20.50.7A t t e n u a t i o n a t 27 M H z −d B

6090

-30-40-10-20102030405070800.60.40.3T −Ambient Temperature −C

A

o 27

28

293133A t t e n u a t i o n a t 74 M H z −d B

6090

-30-40-10-201020304050708030SLOS521A–MARCH 2007–REVISED JANUARY 2008

TYPICAL CHARACTERISTICS (continued)

QUIESCENT CURRENT vs TEMPERATURE

VOLTAGE GAIN vs TEMPERATURE

Figure 22.

Figure 23.

ATTENUATION at 27MHz vs TEMPERATURE

ATTENUATION at 74MHz vs TEMPERATURE

Figure 24.Figure 25.

APPLICATION INFORMATION

OPERATING VOLTAGE

INPUT VOLTAGE

INPUT OVERVOLTAGE PROTECTION

External Input/Output Pin

The THS7316is targeted for standard definition video output buffer applications.Although it can be used for numerous other applications,the needs and requirements of the video signal is an important design parameter of the THS7316.Built on the Silicon Germanium (SiGe)BiCom-3process,the THS7316incorporates many features not typically found in integrated video parts while consuming low power.

The THS7316has the following features:

•Single-Supply 3-V to 5-V operation with low total quiescent current of 18.3-mA at 3.3-V and 19.3-mA at 5-V.•Input configuration accepting DC +Level shift,AC Sync-Tip Clamp.

•AC-Biasing is accomplished with the use of an external pull-up resistor to the positive power supply.•5th -Order Low Pass Filter for DAC reconstruction or ADC image rejection:

–36-MHz for HDTV,Y'P'B P'R 720p/1080i,G'B'R'(R'G'B'),and Computer VGA/SVGA/XGA signals.

–Can also be used for SDTV (480i,576i,CVBS,S-Video),and EDTV (480p and 576p)signals if desired.•Internal fixed gain of 2V/V (6dB)buffer that can drive up to 2video lines per channel with dc coupling or traditional ac coupling.

•Signal flow-through configuration using an 8-pin SOIC package that complies with the latest (RoHS compatible)and Green manufacturing requirements.

The THS7316is designed to operate from 3-V to 5-V over a –40°C to 85°C temperature range.The impact on performance over the entire temperature range is negligible due to the implementation of thin film resistors and high quality –low temperature coefficient capacitors.

The power supply pins should have a 0.1-µF to 0.01-µF capacitor placed as close as possible to these pins.Failure to do so may result in the THS7316outputs ringing or have an oscillation.Additionally,a large capacitor,such as 22µF to 100µF,should be placed on the power supply line to minimize interference with 50/60Hz line frequencies.

The THS7316input range allows for an input signal range from –0.3V to about (V s+–1.5V).But,due to the internal fixed gain of 2V/V (6dB)and the internal level shift of nominally 140-mV,the output is generally the limiting factor for the allowable linear input range.For example,with a 5-V supply,the linear input range is from –0.3V to 3.5V.However,due to the gain and level shift,the linear output range limits the allowable linear input range to be from about –0.1V to 2.3V.

The THS7316is built using a high-speed complementary bipolar and CMOS process.The internal junction breakdown voltages are low for these small geometry devices.These breakdowns are reflected in the Absolute Maximum Ratings table.All input and output device pins are protected with internal ESD protection diodes to the power supplies,as shown in Figure 26.

Figure 26.Internal ESD Protection

TYPICAL CONFIGURATION and VIDEO TERMINOLOGY

DAC/Encoder

75W

HDTV 720p/1080i Y’P’P’G’B’R’VGA SVGA XGA

B R W

75W

SLOS521A–MARCH 2007–REVISED JANUARY 2008

These diodes provide moderate protection to input overdrive voltages above and below the supplies as well.The protection diodes can typically support 30-mA of continuous current when overdriven.

A typical application circuit using the THS7316as a video buffer is shown in Figure 27.It shows a DAC (or encoder such as the THS8200)driving the three input channels of the these channels show HDTV Y'P'

B P'R (sometimes labeled Y'C'B C'R )signals of a 720p or 1080i system,they can also be G'B'R'(R'G'B')signals or other variations.

Note that the Y'term is used for the luma channels throughout this document rather than the more common luminance (Y)term.The reason is to account for the definition of luminance as stipulated by the CIE –International Commission on Illumination.Video departs from true luminance since a nonlinear term,gamma,is added to the true RGB signals to form R'G'B'signals.These R'G'B'signals are then used to mathematically create luma (Y').Thus luminance (Y)is not maintained providing a difference in terminology.

This rationale is also used for the chroma (C')term.Chroma is derived from the non-linear R'G'B'terms and thus it is nonlinear.Chrominance (C)is derived from linear RGB giving the difference between chroma (C')and chrominance (C).The color difference signals (P'B /P'R /U'/V')are also referenced this way to denote the nonlinear (gamma corrected)signals.

R'G'B'(commonly mislabeled RGB)is also called G’B’R’(again commonly mislabeled as GBR)in professional video systems.The SMPTE component standard stipulates that the luma information is placed on the first channel,the blue color difference is placed on the second channel,and the red color difference signal is placed on the third channel.This is consistent with the Y'P'B P'R nomenclature.Because the luma channel (Y')carries the sync information and the green channel (G')also carries the sync information,it makes logical sense that G'be placed first in the system.Since the blue color difference channel (P'B )is next and the red color difference channel (P'R )is last,then it also makes logical sense to place the B'signal on the second channel and the R'signal on the third channel,respectively .Thus hardware compatibility is better achieved when using G'B'R'rather than R'G'B'.Note that for many G'B'R'systems sync is embedded on all three channels,but may not always be the case in all systems.

Figure 27.Typical HDTV Y'/P'B /P'R Inputs From DC-Coupled Encoder/DAC

With AC-Coupled Line Driving

INPUT MODE OF OPERATION –DC

Input

The inputs to the THS7316allows for both ac-coupled and dc-coupled inputs.Many DACs or Video Encoders can be dc connected to the THS7316.One of the drawbacks to dc coupling is when 0-V is applied to the input.Although the input of the THS7316allows for a 0-V input signal with no issues,the output swing of a traditional amplifier cannot yield a 0-V signal resulting in possible clipping.This is true for any single-supply amplifier due to the limitations of the output transistors.Both CMOS and bipolar transistors cannot go to 0-V while sinking current.This trait of a transistor is also the same reason why the highest output voltage is always less than the power supply voltage when sourcing current.

This output clipping can reduce the sync amplitudes (both horizontal and vertical sync amplitudes)on the video signal.A problem occurs if the receiver of this video signal uses an AGC loop to account for losses in the transmission line.Some video AGC circuits derive gain from the horizontal sync amplitude.If clipping occurs on the sync amplitude,then the AGC circuit can increase the gain too much –resulting in too much amplitude gain correction.This may result in a picture with an overly bright display with too much color saturation.

It is good engineering design practice to ensure saturation/clipping does not take place.Transistors always take a finite amount of time to come out of saturation.This saturation could possibly result in timing delays or other aberrations on the signals.

To eliminate saturation/clipping problems,the THS7316has a dc +140-mV input shift feature.This feature takes the input voltage and adds an internal +140-mV shift to the signal.Since the THS7316also has a gain of 6dB (2V/V),the resulting output with a 0-V applied input signal is about 280-mV.The THS7316rail-to-rail output stage can create this output level while connected to a typical video load.This ensures that no saturation /clipping of the sync signals occur.This is a constant shift regardless of the input signal.For example,if a 1-V input is applied,the output is at 2.28-V.

Because the internal gain is fixed at 6dB,the gain dictates what the allowable linear input voltage range can be without clipping concerns.For example,if the power supply is set to 3-V,the maximum output is about 2.9-V while driving a significant amount of current.Thus,to avoid clipping,the allowable input is ((2.9V /2)–0.14V)=

1.31V.This is true for up to the maximum recommended 5-V power supply that allows about a ((4.9V /2)–0.14V)=

2.31V input range while avoiding clipping on the output.

The input impedance of the THS7316in this mode of operation is dictated by the internal 800-k Ωpull-down resistor.This is shown in Figure 28.Note that the internal voltage shift does not appear at the input pin,only the output pin.

Figure 28.Equivalent DC Input Mode Circuit

INPUT MODE OF OPERATION –AC SYNC TIP CLAMP

Input

SLOS521A–MARCH 2007–REVISED JANUARY 2008Some video DACs or encoders are not referenced to ground but rather to the positive power supply.These DACs typically only sink current rather than the more traditional current sourcing DAC where the resistor is referenced to ground.The resulting video signals can be too high of a voltage for a dc-coupled video buffer to function properly.To account for this scenario the THS7316incorporates a sync-tip clamp circuit.This function requires a capacitor (nominally 0.1µF)to be in series with the input.Note,while the term sync-tip-clamp is used throughout this document,it should be noted that the THS7316is better termed as a dc-restoration circuit based on how this function is performed.This circuit is an active clamp circuit and not a passive diode clamp function.The input to the THS7316has an internal control loop which sets the lowest input applied voltage to clamp at ground (0-V).By setting the reference at 0-V,the THS7316allows a dc-coupled input to also function.Hence,the STC is considered transparent since it does not operate unless the input signal goes below ground.The signal then goes through the same 140-mV level shifter resulting in an output voltage low level of 280-mV.If the input signal tries to go below the 0-V,the internal control loop of the THS7316will source up to 3-mA of current to increase the input voltage level on the THS7316input side of the coupling capacitor.As soon as the voltage goes above the 0-V level,the loop stops sourcing current and becomes high impedance.

One of the concerns about the sync-tip-clamp level is how the clamp reacts to a sync edge that has overshoot—common in VCR signals or reflections found in poor PCB layouts.Ideally the STC should not react to the overshoot voltage of the input signal.Otherwise,this could result in clipping on the rest of the video signal as it may raise the bias voltage too much.

To help minimize this input signal overshoot problem,the control loop in the THS7316has an internal low-pass filter as shown in Figure 29.This filter reduces the response time of the STC circuit.This delay is a function of how far the ground,but in general it is about a 80-ns delay.The effect of this filter is to slow down the response of the control loop so as not to clamp on the input overshoot voltage,but rather the flat portion of the sync signal.

As a result of this delay,the sync may have an apparent voltage shift.The amount of shift is dependant upon the amount of droop in the signal as dictated by the input capacitor and the STC current flow.Because the sync is primarily for timing purposes with syncing occurring on the edge of the sync signal,this shift is transparent in most systems.

While this feature may not fully eliminate overshoot issues on the input signal for excessive overshoot and/or ringing,the STC system should help minimize improper clamping levels.As an additional method to help minimize this issue,an external capacitor (ex:10pF to 47pF)to ground in parallel with the external termination resistors can help filter overshoot problems.

It should be noted that this STC system is dynamic and does not rely upon timing in any way.It only depends on the voltage appearing at the input pin at any given point in time.The STC filtering helps minimize level shift problems associated with switching noises or very short spikes on the signal line.This helps ensure a very robust STC system.

Figure 29.Equivalent AC Sync Tip Clamp Input Circuit

When the AC Sync-Tip-Clamp (STC)operation is used,there must also be some finite amount of discharge bias

But,what happens if the input signal goes above the0-V input level?The problem is the video signal is always above this level,and must not be altered in any way.But if the Sync level of the input signal is above this0-V level,then the internal discharge(sink)current will discharge the ac-coupled bias signal to the proper0-V level. This discharge current must not be large enough to alter the video signal appreciably,or picture quality issues may arise.This is often seen by looking at the tilt(aka droop)of a constant luma signal being applied and looking at the resulting output level.The associated change in luma level from the beginning of the video line to the end of the video line is the amount of line tilt(droop).

If the discharge current is small,the amount of tilt is low which is good.But,the amount of time for the system to capture the sync signal could be too long.This is also termed hum rejection.Hum arises from the ac line voltage frequency of50-Hz or60-Hz.The value of the discharge current and the ac-coupling capacitor combine to dictate the hum rejection and the amount of line tilt.

To allow for both dc-coupling and ac-coupling in the same part,the THS7316incorporates an800-kΩresistor to ground.Although a true constant current sink is preferred over a resistor,there are significant issues when the voltage is near ground.This can cause the current sink transistor to saturate and cause potential problems with the signal.This resistor is large enough as to not impact a dc-coupled DAC termination.For discharging an ac-coupled source,Ohm’s Law is used.If the video signal is1V,then there is1V/800kΩ=1.25-µA of discharge current.If more hum rejection is desired or there is a loss of sync occurring,then decrease the0.1-µF input coupling capacitor.A decrease from0.1µF to0.047µF increases the hum rejection by a factor of2.1. Alternatively an external pull-down resistor to ground may be added which decreases the overall resistance,and ultimately increases the discharge current.

To ensure proper stability of the AC STC control loop,the source impedance must be less than1-kΩwith the input capacitor in place.Otherwise,there is a possibility of the control loop to ring and this ringing may appear on the output of the THS7316.Because most DACs or encoders use resistors to establish the voltage,which are typically less than300-Ω,then meeting the<1-kΩrequirement is done.But,if the source impedance looking from the THS7316input perspective is high,then add a1-kΩresistor to GND to ensure proper operation of the THS7316.

INPUT MODE OF OPERATION–AC BIAS

Sync tip clamps work well for signals that have horizontal and/or vertical syncs associated with them.But,some video signals do not have a sync embedded within the signal–such as Chroma or the P’B and P’R channels of a 480i/480p/576i/576p signal;or the bottom of the sync is not the lowest possible level of the video signal–such as the P’B and P’R channels of a720p and1080i signal.If ac-coupling of these signals is desired,then a dc bias is required to properly set the dc operating point within the THS7316.This function is easily accomplished with the THS7316by adding an external pull-up resistor to the positive power supply as shown in Figure30.

Input

OUTPUT MODE OF OPERATION –DC COUPLED SLOS521A–MARCH 2007–REVISED JANUARY 2008(1)R PU denotes an external Pull-up Resistor

Figure 30.AC-Bias Input Mode Circuit Configuration

The dc voltage appearing at the input pin is approximately equal to:

V DC =V S +×(800k ÷(800k +R PU ))

The THS7316allowable input range is approximately (V S +–1.5V)which allows for a wide input voltage range.As such,the input dc-bias point is flexible with the output dc-bias point being the primary factor.For example,if the output dc-bias point is desired to be 1.65V on a 3.3-V supply,then the input dc-bias point should be (1.65V –280mV)/2=0.685V.Thus,the pull-up resistor calculates to about 3.01-M Ωresulting in 0.693V.If the input dc-bias point is desired to be 0.685V with a 5-V power supply,then the pull-up resistor calculates to about

5.1M Ω.

The internal 800-k Ωresistor has approximately a ±20%variance.As such,the calculations should take this into account.For the 0.693V example above using an ideal 3.01-M Ωresistor,the input dc-bias voltage is about 0.693V ±0.11V.

One other issue that must be taken into account is that the dc-bias point is a function of the power supply.As such,there may be an impact on power supply rejection (PSRR)on the system.To help reduce the impact,the input capacitor combined with the pull-up resistance functions as a low-pass filter.Additionally,the time to charge the capacitor to the final dc-bias point is also a function of the pull-up resistor and the input capacitor.Lastly,the input capacitor forms a high-pass filter with the parallel impedance of the pull-up resistor and the 800-k Ωresistor.It is good to have this high pass filter at about 3-Hz to minimize any potential droop on a P'B ,P'R ,or non-sync signals.A 0.1-µF input capacitor with a 3.01-M Ωpull-up resistor equates to about a 2.5-Hz high-pass corner frequency.

This mode of operation is recommended for use with chroma (C'),P’B ,P'R ,U',V',and non-sync B'and/or R'signals.

The THS7316incorporates a rail-to-rail output stage that can be used to drive the line directly without the need for large ac-coupling capacitors as shown in Figure 31.This offers the best line tilt and field tilt (or droop)performance since there is no ac-coupling that if the input is ac-coupled,then the resulting tilt due to the input ac-coupling is seen on the output regardless of the output coupling.The 80-mA output current drive capability of the THS7316was designed to drive two video lines per channel simultaneously –essentially a 75-Ωload –while keeping the output dynamic range as wide as possible.

DAC/

Encoder 75W

HDTV 720p/1080i Y’P’P’G’B’R’VGA SVGA XGA B R W 75W OUTPUT MODE OF OPERATION –AC COUPLED Figure 31.Typical HDTV Y'P'B P'R /G'B'R'System with DC-Coupled Line Driving

One concern of dc-coupling is if the line is terminated to ground.If the ac-bias input configuration is used,the output of the THS7316will have a dc-bias on the output.With 2lines terminated to ground,this creates a dc-current path to exist which results in a slightly decreased high output voltage swing and resulting in an increase in power dissipation of the THS7316.While the THS7316was designed to operate with a junction temperature of up to 125°C,care must be taken to ensure that the junction temperature does not exceed this level or else long term reliability could suffer.Although this configuration only adds less than 10mW of power dissipation per channel,the overall low power dissipation of the THS7316design minimizes potential thermal issues even when using the SOIC package at high ambient temperatures.

Another concern of dc coupling is the blanking level voltage of the video signal.The EIA specification dictates that the blanking level shall be 0V ±1V.While there is some question as to whether this voltage is at the output of the amplifier or at the receiver,it is generally regarded to be measured at the receiver side of a system as the rest of the specification voltage requirements are given with doubly terminated connections present.With the rail-to-rail output swing capability,combined with the 140-mV input level shift,meeting this requirement is accomplished.Thus,elimination of the large output ac-coupling capacitor can be done while still meeting the EIA specification.This can save significant PCB area and costs.

Note that the THS7316can drive the line with dc-coupling regardless of the input mode of operation.The only requirement is to make sure the video line has proper termination in series with the output –typically 75-Ω.This helps isolate capacitive loading effects from the THS7316output.Failure to isolate capacitive loads may result in instabilities with the output buffer potentially causing ringing or oscillations to appear.The stray capacitance appearing directly at the THS7316output pins should be kept below 20-pF.

The most common method of coupling the video signal to the line is with the use of a large capacitor.This capacitor is typically between 220-µF and 1000-µF,although 330-µF is common.This value of this capacitor must be this large to minimize the line tilt (droop)and/or field tilt associated with ac-coupling as described previously in this document.AC-coupling is done for several reasons,but the most common reason is to ensure full inter-operability with the receiving video system.This ensures that regardless of the reference dc voltage used on the transmit side,the receive side will re-establish the dc reference voltage to its own requirements,and meets EIA specifications.

Like the dc-output mode of operation,each line should have a 75-Ωsource termination resistor in series with the ac-coupling capacitor.If 2lines are to be driven,it is best to have each line use its own capacitor and resistor rather than sharing these components as shown in Figure 32.This helps ensure line-to-line dc isolation and the potential problems as stipulated previously.Using a µF capacitor for 2-lines can be done,but there is a chance for interference to be created between the two receivers.

W

W

W

W W

Y’Out 1

W

DAC/

Encoder HDTV 720p/1080i Y’P’P’G’B’R’B R

330f

m SLOS521A–MARCH 2007–REVISED JANUARY 2008Due to the edge rates and frequencies of operation,it is recommended –but not required –to place a 0.1-µF to 0.01-µF capacitor in parallel with the large 220-µF to 1000-µF capacitor.These large value capacitors are most commonly aluminum electrolytic.These capacitors have significantly large ESR (equivalent series resistance),and their impedance at high frequencies is large due to the associated inductances involved with the leads and construction.The small 0.1-µF to 0.01-µF capacitors help pass these high frequency (>1MHz)signals with much lower impedance than the large capacitors.

Although it is common to use the same capacitor values for all the video lines,the frequency bandwidth of the chroma signal in a S-Video system are not required to go as low –or as high of a frequency –as the luma channels.Thus the capacitor values of the chroma line(s)can be smaller –such as 0.1-µF.

A.

Due to the high frequency content of the video signal,it is recommended,but not required,to add a 0.1-µF or 0.01-µF capacitor in parallel with these large capacitors.B.Current sinking DAC /Encoder shown.See the application notes.

Figure 32.Typical 480i/576i Y'P'B P'R AC-Input System Driving 2AC-Coupled Video Lines

www.ti.com

LOW PASS FILTER

THS7316 SLOS521A–MARCH2007–REVISED JANUARY2008

Each channel of the THS7316incorporates a5th-Order Low Pass Filter.These video reconstruction filters minimize DAC images from being passed onto the video receiver.Depending on the receiver design,failure to eliminate these DAC images can cause picture quality problems due to aliasing of the ADC.Another benefit of the filter is to smooth out aberrations in the signal which some DACs can have if their own internal filtering is not good.This helps with picture quality and helps insure the signal meets video bandwidth requirements.

Each filter in the THS7316is associated with a Butterworth characteristic.The benefit of the Butterworth response is that the frequency response is flat with a relatively steep initial attenuation at the corner frequency. The problem is that the group delay rises near the corner frequency.Group delay is defined as the change in phase(radians/second)divided by a change in frequency.An increase in group delay corresponds to a time domain pulse response that has overshoot and some possible ringing associated with the overshoot.

The use of other type of filters,such as elliptic or chebyshev,are not recommended for video applications due to their very large group delay variations near the corner frequency resulting in significant overshoot and ringing. While these elliptic or chebyshev filters may help meet the video standard specifications with respect to amplitude attenuation,their group delay is beyond the standard specifications.Coupled with the fact that video can go from a white pixel to a black pixel over and over again,ringing can occur.Ringing typically causes a display to have ghosting or fuzziness appear on the edges of a sharp transition.However,a Bessel filter has an ideal group delay response,but the rate of attenuation is typically too low for acceptable image rejection.Thus the Butterworth filter is a respectable compromise for both attenuation and group delay.

The THS7316filters have a nominal corner(-3dB)frequency at36-MHz and a–1dB passband typically at 31-MHz.This36-MHz filter is ideal for High Definition(HD)720p and1080i signals.For systems that oversample significantly,the THS7316can also be useful for Standard Definition(SD)NTSC and PAL signals such as 480i/576i Y'P'B P'R,Y'U'V',and broadcast G’B’R’(R’G’B’)signals.It can also be useful with Enhanced Definition (ED)signals including480p/576p Y'P'B P'R,Y'U'V',broadcast G’B’R’(R’G’B’)signals,and computer video signals. The36-MHz-3dB corner frequency was designed to allow a maximally flat video signal while achieving30-dB of attenuation at74.25-MHz–a common sampling frequency between the DAC/ADC2nd and3rd Nyquist zones found in many video systems.This is important because any signal appearing around this frequency can appear in the baseband due to aliasing effects of an analog to digital converter found in a receiver.Keep in mind that DAC images do not stop at74.25MHz,they continue around the sampling frequencies of148.5MHz, 222.75-MHz,297-MHz,etc.Because of these multiple images that an ADC can fold down into the baseband signal,the low pass filter must also eliminate these higher order images.The THS7316has over50-dB attenuation at148.5-MHz,over50-dB attenuation at222.75-MHz,and about55-dB attenuation at297-MHz. Attenuation to1-GHz is at least36-dB which makes sure that images do not effect the desired video baseband signal.

The36-MHz filter frequency was chosen to account for process variations in the THS7316.To ensure the required video frequencies are not affected,the filter corner frequency must be high enough to allow component variations.The other consideration is the attenuation must be large enough to ensure the anti-aliasing/ reconstruction filtering is enough to meet the system demands.Thus,the filter frequencies were not arbitrarily selected.

www.ti.com BENEFITS OVER PASSIVE FILTERING THS7316SLOS521A–MARCH 2007–REVISED JANUARY 2008Two key benefits of using an integrated filter system,such as the THS7316,over a passive system is PCB area and filter variations.The small SOIC-8package (3-video channels)is much smaller over a passive RLC network,especially a 5-pole passive network.Additionally,inductors have at best ±10%tolerances (normally ±15%to ±20%is common)and capacitors typically have ±10%tolerances.Using a Monte Carlo analysis shows that the filter corner frequency (–3dB),flatness (–1dB),Q factor (or peaking),and channel-to-channel delay has wide variations.This can lead to potential performance and quality issues in mass-production environments.The THS7316solves most of these problems by using the corner frequency as essentially the only variable.

One concern about an active filter in an integrated circuit is the variation of the filter characteristics when the ambient temperature and the subsequent die temperature changes.To minimize temperature effects,the THS7316uses low temperature coefficient resistors and high quality –low temperature coefficient capacitors found in the BiCom-3process.The filters have been specified by design to account for process variations and temperature variations to maintain proper filter characteristics.This maintains a low channel-to-channel time delay which is required for proper video signal performance.

Another benefit of a THS7316over a passive RLC filter are the input and output impedances.The input impedance presented to the DAC varies significantly with a passive network and may cause voltage variations over frequency.The THS7316input impedance is 800k Ωand only the 2-pF input capacitance plus the PCB trace capacitance impacting the input impedance.As such,the voltage variation appearing at the DAC output is better controlled with the THS7316.

On the output side of the filter,a passive filter will again have a impedance variation over frequency.The THS7316is an op-amp which approximates an ideal voltage source.A voltage source is desirable because the output impedance is very low and can source and sink current.To properly match the transmission line characteristic impedance of a video line,a 75-Ωseries resistor is placed on the output.To minimize reflections and to maintain a good return loss,this output impedance must maintain a 75-Ωimpedance.A passive filter impedance variation is not specified while the THS7316has approximately 0.5-Ωof output impedance at 10MHz.Thus,the system is matched better with a THS7316compared to a passive filter.

One last benefit of the THS7316over a passive filter is power dissipation.A DAC driving a video line must be able to drive a 37.5-Ωload -the receiver 75-Ωresistor and the 75-Ωimpedance matching resistor next to the DAC to maintain the source impedance requirement.This forces the DAC to drive at least 1.25-V peak (100%Saturation CVBS)/37.5Ω=33.3mA.A DAC is a current steering element and this amount of current flows internally to the DAC even if the output is 0-V.Thus,power dissipation in the DAC may be high -especially when 6-channels are being driven.Using the THS7316,with a high input impedance and the capability to drive up to 2-video lines per channel,can reduce the DAC power dissipation significantly.This is because the resistance the DAC is driving can be substantially increased.It is common to set this in a DAC by a current setting resistor on the DAC.Thus,the resistance can be 300-Ωor more -substantially reducing the current drive demands from the DAC and saving substantial amount of power.For example,a 3.3-V 6-Channel DAC dissipates 660mW just for the steering current capability (6ch x 33.3mA x 3.3V)if it needs to drive 37.5-Ωload.With a 300-Ωload,the DAC power dissipation due to current steering current would only be 82.5mW (6ch X 4.16mA X 3.3V).

www.ti.com EVALUATION MODULE

THS7316SLOS521A–MARCH 2007–REVISED JANUARY 2008

To evaluate the THS7316,an evaluation module (EVM)is available.This allows for testing of the THS7316in many different systems.Inputs and outputs include RCA connectors for consumer grade interconnections,or BNC connectors for higher level lab grade connections.Several unpopulated component pads are found on the EVM to allow for different input and output configurations as dictated by the user.

Figure 33shows the schematic of the THS7316EVM.Figure 34and Figure 35shows the top layer and bottom EVM which incorporates standard bill of materials is shown in Table 1as supplied from Texas Instruments.

Figure 33.THS7316D EVM

www.ti.com THS7316SLOS521A–MARCH 2007–REVISED JANUARY 2008

Figure 34.Top View

Figure 35.Bottom View

PACKAGING INFORMATION Orderable Device

Status (1)Package Type Package Drawing Pins Package Qty Eco Plan (2)Lead/Ball Finish MSL Peak Temp (3)THS7316D

ACTIVE SOIC D 875Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR THS7316DG4

ACTIVE SOIC D 875Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR THS7316DR

ACTIVE SOIC D 82500Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR THS7316DRG4

ACTIVE SOIC D 82500Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR (1)The marketing status values are defined as follows:

ACTIVE:Product device recommended for new designs.

LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.

NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.

PREVIEW:Device has been announced but is not in production.Samples may or may not be available.

OBSOLETE:TI has discontinued the production of the device.

(2)Eco Plan -The planned eco-friendly classification:Pb-Free (RoHS),Pb-Free (RoHS Exempt),or Green (RoHS &no Sb/Br)-please check http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD:The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS):TI's terms "Lead-Free"or "Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all 6substances,including the requirement that lead not exceed 0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1)lead-based flip-chip solder bumps used between the die and package,or 2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free (RoHS compatible)as defined above.

Green (RoHS &no Sb/Br):TI defines "Green"to mean Pb-Free (RoHS compatible),and free of Bromine (Br)and Antimony (Sb)based flame retardants (Br or Sb do not exceed 0.1%by weight in homogeneous material)

(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases

its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 8-Jan-2008

TAPE AND REEL

INFORMATION *All

dimensions are nominal Device Package Type Package Drawing

Pins

SPQ Reel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant THS7316DR SOIC D 82500330.012.4 6.4 5.2 2.1

8.012.0Q1PACKAGE MATERIALS INFORMATION

www.ti.com 11-Mar-2008

*All

dimensions are nominal Device

Package Type Package Drawing Pins SPQ Length (mm)Width (mm)Height (mm)THS7316DR SOIC D 82500346.0346.029.0

PACKAGE MATERIALS INFORMATION

www.ti.com 11-Mar-2008Pack Materials-Page 2

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