LP38692_电源芯片

LP38690-ADJ/LP38692-ADJ

1A Low Dropout CMOS Linear Regulators with Adjustable Output

Stable with Ceramic Output Capacitors

General Description

The LP38690/2-ADJ low dropout CMOS linear regulators provide 2.5%precision reference voltage,extremely low dropout voltage (450mV @1A load current,V OUT =5V)and excellent AC performance utilizing ultra low ESR ceramic output capacitors.

The low thermal resistance of the LLP and SOT-223pack-ages allow the full operating current to be used even in high ambient temperature environments.

The use of a PMOS power transistor means that no DC base drive current is required to bias it allowing ground pin current to remain below 100µA regardless of load current,input voltage,or operating temperature.

Dropout Voltage:450mV (typ)@1A (typ.5V out).Ground Pin Current:55µA (typ)at full load.Adjust Pin Voltage:2.5%(25˚C)accuracy.

Features

n Output voltage range of 1.25V -9V

n 2.5%adjust pin voltage accuracy (25˚C)

n Low dropout voltage:450mV @1A (typ,5V out)n Wide input voltage range (2.7V to 10V)n Precision (trimmed)bandgap reference n Guaranteed specs for -40˚C to +125˚C n 1µA off-state quiescent current n Thermal overload protection n Foldback current limiting

n SOT-223and 6-Lead LLP packages n

Enable pin (LP38692-ADJ)

Applications

n Hard Disk Drives n Notebook Computers n Battery Powered Devices n

Portable Instrumentation

Typical Application Circuits

20126701

20126702

V OUT =V ADJ x (1+R1/R2)

Note:*Minimum value required for stability.

January 2005

LP38690-ADJ/LP38692-ADJ 1A Low Dropout CMOS Linear Regulators with Adjustable Output Stable with Ceramic Output Capacitors

©2005National Semiconductor Corporation DS201267www.national.com

Connection Diagrams

20126703

SOT-223,Top View LP38692MP-ADJ

201267046-Lead LLP,Bottom View

LP38690SD-ADJ 20126705

6-Lead LLP,Bottom View

LP38692SD-ADJ

Pin Description

PIN DESCRIPTION

V IN This is the input supply voltage to the regulator.For LLP package devices,both V IN pins must be tied together for full current operation (500mA maximum per pin).

GND Circuit ground for the regulator.This is connected to the die through the lead frame,and also functions as the heat sink when the large ground pad is soldered down to a copper plane.V OUT Regulated output voltage.

V EN The enable pin allows the part to be turned ON and OFF by pulling this pin high or low.

ADJ

The adjust pin is used to set the regulated output voltage by connecting it to the external resistors R1and R2(see Typical Application Circuit).

Ordering Information

Order Number Package Marking

Package Type Package Drawing

Supplied As LP38690SD-ADJ L112B 6-Lead LLP SDE06A 1000Units Tape and Reel LP38692SD-ADJ L122B 6-Lead LLP SDE06A 1000Units Tape and Reel LP38692MP-ADJ LJNB SOT-223MP05A 1000Units Tape and Reel LP38690SDX-ADJ L112B 6-Lead LLP SDE06A 4500Units Tape and Reel LP38692SDX-ADJ L122B 6-Lead LLP SDE06A 4500Units Tape and Reel LP38692MPX-ADJ

LJNB

SOT-223

MP05A

2000Units Tape and Reel

L P 38690-A D J /L P 38692-A D J

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If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

Storage Temperature Range−65˚C to+150˚C Lead Temp.(Soldering,5seconds)260˚C ESD Rating(Note3)2kV Power Dissipation(Note2)Internally Limited V(max)All pins(with respect to GND)-0.3V to12V

I OUT Internally Limited Junction Temperature−40˚C to+150˚C

Operating Ratings

V IN Supply Voltage 2.7V to10V Operating Junction

Temperature Range

−40˚C to+125˚C

Electrical Characteristics Limits in standard typeface are for T

J

=25˚C,and limits in boldface type apply over the full operating temperature range.Unless otherwise specified:V IN=V OUT+1V,C IN=C OUT=10µF,I LOAD=10mA. Min/Max limits are guaranteed through testing,statistical correlation,or design.

Symbol Parameter Conditions Min

Typ

(Note4)

Max Units

V ADJ ADJ Pin Voltage V IN=2.7V 1.219 1.25 1.281

V 3.2V≤V IN≤10V

100µA1.187 1.25 1.313

∆V O/∆V IN Output Voltage Line Regulation

(Note6)V O+0.5V≤V IN≤10V

I L=25mA

0.030.1%/V

∆V O/∆I L Output Voltage Load Regulation

(Note7)1mAV IN=V O+1V

1.85%/A

V IN-V O Dropout Voltage(Note8)(V O=1.8V)

I L=1A

9501600

mV (V O=2.5V)

I L=0.1A

I L=1A

80

800

145

1300

(V O=3.3V)

I L=0.1A

I L=1A

65

650

110

1000

(V O=5V)

I L=0.1A

I L=1A

45

450

100

800

I Q Quiescent Current V IN≤10V,I L=100µA-1A55100

µA

V EN≤0.4V,(LP38692-ADJ Only)0.0011

I L(MIN)Minimum Load Current V IN-V O≤4V100

I FB Foldback Current Limit V IN-V O>5V450

mA

V IN-V O<4V1500

PSRR Ripple Rejection V IN=V O+2V(DC),with1V(p-p)/

120Hz Ripple

55dB

T SD Thermal Shutdown Activation

(Junction Temp)160

˚C

T SD (HYST)Thermal Shutdown Hysteresis

(Junction Temp)

10

I ADJ ADJ Input Leakage Current V ADJ=0-1.5V

V IN=10V

-1000.01100nA

LP38690-ADJ/LP38692-ADJ

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Electrical Characteristics Limits in standard typeface are for T J =25˚C,and limits in boldface type apply

over the full operating temperature range.Unless otherwise specified:V IN =V OUT +1V,C IN =C OUT =10µF,I LOAD =10mA.Min/Max limits are guaranteed through testing,statistical correlation,or design.(Continued)Symbol Parameter

Conditions

Min

Typ (Note 4)Max

Units e n

Output Noise

BW =10Hz to 10kHz V O =3.3V

0.7µV/V O (LEAK)Output Leakage Current V O =V O (NOM)+1V @10V IN 0.5

2µA

V EN

Enable Voltage (LP38692-ADJ Only)

Output =OFF

0.4

V

Output =ON,V IN =4V 1.8Output =ON,V IN =6V 3.0Output =ON,V IN =10V

4.0I EN

Enable Pin Leakage (LP38692-ADJ Only)

V EN =0V or 10V,V IN =10V

-1

0.001

1

µA

Note 1:Absolute maximum ratings indicate limits beyond which damage to the component may occur.Operating ratings indicate conditions for which the device is intended to be functional,but do not guarantee specific performance limits.For guaranteed specifications,see Electrical Characteristics.Specifications do not apply when operating the device outside of its rated operating conditions.

Note 2:At elevated temperatures,device power dissipation must be derated based on package thermal resistance and heatsink values (if a heatsink is used).The junction-to-ambient thermal resistance (θJ-A )for the SOT-223is approximately 125˚C/W for a PC board mounting with the device soldered down to minimum copper area (less than 0.1square inch).If one square inch of copper is used as a heat dissipator for the SOT-223,the θJ-A drops to approximately 70˚C/W.The θJ-A values for the LLP package are also dependent on trace area,copper thickness,and the number of thermal vias used (refer to application note AN-1187).If power disspation causes the junction temperature to exceed specified limits,the device will go into thermal shutdown.

Note 3:ESD is tested using the human body model which is a 100pF capacitor discharged through a 1.5k resistor into each pin.Note 4:Typical numbers represent the most likely parametric norm for 25˚C operation.

Note 5:If used in a dual-supply system where the regulator load is returned to a negative supply,the output pin must be diode clamped to ground.Note 6:Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage.

Note 7:Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from 1mA to full load.Note 8:Dropout voltage is defined as the minimum input to output differential required to maintain the output within 100mV of nominal value.

L P 38690-A D J /L P 38692-A D J

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Block Diagrams

20126706

FIGURE 1.LP38690-ADJ Functional Diagram (LLP)

20126707

FIGURE 2.LP38692-ADJ Functional Diagram (SOT-223,LLP)

LP38690-ADJ/LP38692-ADJ

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Typical Performance Characteristics

Unless otherwise specified:T J =25˚C,C IN =C OUT =10µF,

enable pin is tied to V IN

(LP38692-ADJ only),V O =1.25V,V IN =2.7V,I L =10mA.

Noise vs Frequency

Noise vs Frequency

20126735

20126736

Noise vs Frequency Ripple Rejection

20126737

20126717

Ripple Rejection Ripple Rejection

20126719

20126721

L P 38690-A D J /L P 38692-A D J

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Typical Performance Characteristics Unless otherwise specified:T

J

=25˚C,C IN=C OUT=10µF, enable pin is tied to V IN(LP38692-ADJ only),V O=1.25V,V IN=2.7V,I L=10mA.(Continued)

V ADJ vs Temperature Line Transient Response

20126730

20126723 Line Transient Response Line Transient Response

2012672420126725 Line Transient Response Line Transient Response

2012672620126727LP38690-ADJ/LP38692-ADJ

Typical Performance Characteristics Unless otherwise specified:T J =25˚C,C IN =C OUT =10µF,

enable pin is tied to V IN (LP38692-ADJ only),V O =1.25V,V IN =2.7V,I L =10mA.(Continued)

Line Transient Response

Load Transient Response

20126728

20126740

Load Transient Response Load Transient Response

2012674120126742

Load Transient Response Load Transient Response

2012674320126744

L P 38690-A D J /L P 38692-A D J

J

=25˚C,C IN=C OUT=10µF, enable pin is tied to V IN(LP38692-ADJ only),V O=1.25V,V IN=2.7V,I L=10mA.(Continued)

Minimum V IN vs I OUT Dropout Voltage vs I OUT

20126750

20126751 Enable Voltage vs Temperature Load Regulation vs Temperature

2012675320126754 Line Regulation vs Temperature

20126755LP38690-ADJ/LP38692-ADJ

Application Hints

EXTERNAL CAPACITORS

Like any low-dropout regulator,external capacitors are re-quired to assure stability.These capacitors must be correctly selected for proper performance.

INPUT CAPACITOR:An input capacitor of at least 1µF is required (ceramic recommended).The capacitor must be located not more than one centimeter from the input pin and returned to a clean analog ground.

OUTPUT CAPACITOR:An output capacitor is required for loop stability.It must be located less than 1centimeter from the device and connected directly to the output and ground pins using traces which have no other currents flowing through them.

The minimum amount of output capacitance that can be used for stable operation is 1µF.Ceramic capacitors are recommended (the LP38690/2-ADJ was designed for use with ultra low ESR capacitors).The LP38690/2-ADJ is stable with any output capacitor ESR between zero and 100Ohms.SETTING THE OUTPUT VOLTAGE:The output voltage is set using the external resistors R1and R2(see Typical Application Circuit).The output voltage will be given by the equation:

V OUT =V ADJ X (1+R1/R2)

Because the part has a minimum load current requirement of 100µA,it is recommended that R2always be 12k Ohms or less to provide adequate loading.Even if a minimum load is always provided by other means,it is not recommended that very high value resistors be used for R1and R2because it can make the ADJ node susceptible to noise pickup.A maximum value of 100k is recommended for R2to prevent this from occurring.

ENABLE PIN (LP38692-ADJ only):The LP38692-ADJ has an enable pin which turns the regulator output on and off.Pulling the enable pin down to a logic low will turn the part off.The voltage the pin has to be pulled up to in order to assure the part is on depends on input voltage (refer to Electrical Characteristics section).This pin should be tied to V IN if the enable function is not used.

FOLDBACK CURRENT LIMITING:Foldback current limit-ing is built into the LP38690/2-ADJ which reduces the amount of output current the part can deliver as the output voltage is reduced.The amount of load current is dependent on the differential voltage between V IN and V OUT .Typically,when this differential voltage exceeds 5V,the load current will limit at about 450mA.When the V IN -V OUT differential is reduced below 4V,load current is limited to about 1500mA.SELECTING A CAPACITOR

It is important to note that capacitance tolerance and varia-tion with temperature must be taken into consideration when selecting a capacitor so that the minimum required amount of capacitance is provided over the full operating tempera-ture range.

Capacitor Characteristics

CERAMIC:For values of capacitance in the 10to 100µF range,ceramics are usually larger and more costly than tantalums but give superior AC performance for bypassing high frequency noise because of very low ESR (typically less than 10m Ω).However,some dielectric types do not have good capacitance characteristics as a function of voltage and temperature.

Z5U and Y5V dielectric ceramics have capacitance that drops severely with applied voltage.A typical Z5U or Y5V capacitor can lose 60%of its rated capacitance with half of the rated voltage applied to it.The Z5U and Y5V also exhibit a severe temperature effect,losing more than 50%of nomi-nal capacitance at high and low limits of the temperature range.

X7R and X5R dielectric ceramic capacitors are strongly rec-ommended if ceramics are used,as they typically maintain a capacitance range within ±20%of nominal over full operat-ing ratings of temperature and voltage.Of course,they are typically larger and more costly than Z5U/Y5U types for a given voltage and capacitance.

TANTALUM:Solid Tantalum capacitors have good tempera-ture stability:a high quality Tantalum will typically show a capacitance value that varies less than 10-15%across the full temperature range of -40˚C to 125˚C.ESR will vary only about 2X going from the high to low temperature limits.The increasing ESR at lower temperatures can cause oscil-lations when marginal quality capacitors are used (if the ESR of the capacitor is near the upper limit of the stability range at room temperature).

PCB LAYOUT

Good PC layout practices must be used or instability can be induced because of ground loops and voltage drops.The input and output capacitors must be directly connected to the input,output,and ground pins of the regulator using traces which do not have other currents flowing in them (Kelvin connect).

The best way to do this is to lay out C IN and C OUT near the device with short traces to the V IN ,V OUT ,and ground pins.The regulator ground pin should be connected to the exter-nal circuit ground so that the regulator and its capacitors have a "single point ground".

It should be noted that stability problems have been seen in applications where "vias"to an internal ground plane were used at the ground points of the IC and the input and output capacitors.This was caused by varying ground potentials at these nodes resulting from current flowing through the ground plane.Using a single point ground technique for the regulator and it’s capacitors fixed the problem.Since high current flows through the traces going into V IN and coming from V OUT ,Kelvin connect the capacitor leads to these pins so there is no voltage drop in series with the input and output capacitors.

RFI/EMI SUSCEPTIBILITY

RFI (radio frequency interference)and EMI (electromagnetic interference)can degrade any integrated circuit’s perfor-mance because of the small dimensions of the geometries inside the device.In applications where circuit sources are present which generate signals with significant high fre-quency energy content (>1MHz),care must be taken to ensure that this does not affect the IC regulator.

If RFI/EMI noise is present on the input side of the regulator (such as applications where the input source comes from the output of a switching regulator),good ceramic bypass ca-pacitors must be used at the input pin of the IC.

If a load is connected to the IC output which switches at high speed (such as a clock),the high-frequency current pulses required by the load must be supplied by the capacitors on the IC output.Since the bandwidth of the regulator loop is less than 100kHz,the control circuitry cannot respond to

L P 38690-A D J /L P 38692-A D J

load changes above that frequency.This means the effective output impedance of the IC at frequencies above100kHz is determined only by the output capacitor(s).

In applications where the load is switching at high speed,the output of the IC may need RF isolation from the load.It is recommended that some inductance be placed between the output capacitor and the load,and good RF bypass capaci-tors be placed directly across the load.

PCB layout is also critical in high noise environments,since RFI/EMI is easily radiated directly into PC traces.Noisy circuitry should be isolated from"clean"circuits where pos-sible,and grounded through a separate path.At MHz fre-quencies,ground planes begin to look inductive and RFI/ EMI can cause ground bounce across the ground plane.In multi-layer PCB applications,care should be taken in layout so that noisy power and ground planes do not radiate directly into adjacent layers which carry analog power and ground.OUTPUT NOISE

Noise is specified in two ways-Spot Noise or Output Noise density is the RMS sum of all noise sources,measured at

the regulator output,at a specific frequency(measured with

a1Hz bandwidth).This type of noise is usually plotted on a

curve as a function of frequency.Total Output Noise or

Broad-Band Noise is the RMS sum of spot noise over a specified bandwidth,usually several decades of frequencies. Attention should be paid to the units of measurement.Spot

noise is measured in unitsµV/root-Hz or nV/root-Hz and total

output noise is measured inµV(rms)

The primary source of noise in low-dropout regulators is the internal reference.Noise can be reduced in two ways:by increasing the transistor area or by increasing the current

drawn by the internal reference.Increasing the area will decrease the chance of fitting the die into a smaller package. Increasing the current drawn by the internal reference in-creases the total supply current(ground pin current).

LP38690-ADJ/LP38692-ADJ

Physical Dimensions

inches (millimeters)unless otherwise noted

6-lead,LLP Package

NS Package Number SDE06A

SOT-223Package

NS Package Number MP05A

L P 38690-A D J /L P 38692-A D J

Notes

National does not assume any responsibility for use of any circuitry described,no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

For the most current product information visit us at www.national.com.

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1.Life support devices or systems are devices or systems

which,(a)are intended for surgical implant into the body,or

(b)support or sustain life,and whose failure to perform when

properly used in accordance with instructions for use provided in the labeling,can be reasonably expected to result in a significant injury to the user.2.A critical component is any component of a life support

device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,or to affect its safety or effectiveness.

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www.national.com LP38690-ADJ/LP38692-ADJ 1A Low Dropout CMOS Linear Regulators with Adjustable Output Stable with Ceramic Output Capacitors