| Priority | Interrupt | Description | Sensitivity |
| 63 (highest) | DBG | Debug exception. See "Emulation Exception Interrupt". | edge |
| 62 | SW | Software exception. See "Software Exception Interrupts". | edge |
| 61–58 | Reserved | Reserved | |
| 57 | HWERR | Hardware error. See "Hardware Error Interrupt". | level |
| 56–54 | Reserved | Reserved | |
| 53 | TIMER1H | Timer 1 high priority. See "Timer Expired Interrupts". | edge |
| 52 | TIMER0H | Timer 0 high priority | edge |
| 51 | Reserved | Reserved | |
| 50 | BUSLOCK | Buslock. See "Bus Lock Interrupt Register". | edge |
| 49 | Reserved | Reserved | |
| 48 | VIRPT | Vector Interrupt. See "Vector Interrupt". | edge |
| 47–45 | Reserved | Reserved | |
| 44 | IRQ3 | IRQ3 pin. See "External (IRQ3–0) Input Interrupts". | edge or level |
| 43 | IRQ2 | IRQ2 pin | edge or level |
| 42 | IRQ1 | IRQ1 pin | edge or level |
| 41 | IRQ0 | IRQ0 pin | edge or level |
| 40–39 | Reserved | Reserved | |
| 38 | DMA13 | DMA channel 13 complete. See "DMA Complete Interrupts". | edge |
| 37 | DMA12 | DMA channel 12 complete. | edge |
| 36–33 | Reserved | Reserved | |
| 32 | DMA11 | DMA channel 11 complete | edge |
| 31 | DMA10 | DMA channel 10 complete | edge |
| 30 | DMA9 | DMA channel 9 complete | edge |
| 29 | DMA8 | DMA channel 8 complete | edge |
| 28–26 | Reserved | Reserved | |
| 25 | DMA7 | DMA channel 7 complete | edge |
| 24 | DMA6 | DMA channel 6 complete | edge |
| 23 | DMA5 | DMA channel 5 complete | edge |
| 22 | DMA4 | DMA channel 4 complete | edge |
| 21–18 | Reserved | Reserved | |
| 17 | DMA3 | DMA channel 3 complete | edge |
| 16 | DMA2 | DMA channel 2 complete | edge |
| 15 | DMA1 | DMA channel 1 complete | edge |
| 14 | DMA0 | DMA channel 0 complete | edge |
| 13–10 | Reserved | Reserved | |
| 9 | LINK3 | Link port 3 request. See "Link Port Service Request Interrupts". | level |
| 8 | LINK2 | Link port 2 request | level |
| 7 | LINK1 | Link port 1 request | level |
| 6 | LINK0 | Link port 0 request | level |
| 5–4 | Reserved | Reserved | |
| 3 | TIMER1L | Timer 1 low priority. See "Timer Expired Interrupts". | edge |
| 2 | TIMER0L | Timer 0 low priority | edge |
| 1 | Reserved | Reserved | |
| 0 (lowest) | KERNEL | Kernel. See "Kernel Interrupt" | edge |
TS201 DMA通道号
| DMA Channel | TCB Registers | Description |
| 0 | DCS0 DCD0 | External port channel 0 source TCB External port channel 0 destination TCB |
| 1 | DCS1 DCD1 | External port channel 1 source TCB External port channel 1 destination TCB |
| 2 | DCS2 DCD2 | External port channel 2 source TCB External port channel 2 destination TCB |
| 3 | DCS3 DCD3 | External port channel 3 source TCB External port channel 3 destination TCB |
| 4 | DC4 | Link port 0 transmit TCB |
| 5 | DC5 | Link port 1 transmit TCB |
| 6 | DC6 | Link port 2 transmit TCB |
| 7 | DC7 | Link port 3 transmit TCB |
| 8 | DC8 | Link port 0 receive TCB |
| 9 | DC9 | Link port 1 receive TCB |
| 10 | DC10 | Link port 2 receive TCB |
| 11 | DC11 | Link port 3 receive TCB |
| 12 | DC12 | AutoDMA channel 0 TCB |
| 13 | DC13 | AutoDMA channel 1 TCB |
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