Entity(实体)
用来说明模型的外部输入输出特征
Architecture(构造体)
用来定义模型的内容和功能
每一个构造体必须有一个实体与它相对应,所以两者一般成对出现
端口模式:
IN: 数据只能从端口流入实体
OUT: 数据只能从端口流出实体
INOUT: 数据从端口流入或流出实体
BUFFER: 数据从端口流出实体,同时可被内部反馈
数据类型:
●BIT :位类型,其值只能为 ‘0’或 '1‘
●BIT_VECTOR :位矢量类型,是基于BIT数据类型的数组。使用位矢量必须注明宽度,即数组中的元素个数和排列。
●BOOLEAN:布尔类型,其值可为 ‘TRUE’或‘FALSE’
●INTEGER:整型,范围为-2147837到2147837(232-1),综合时,要对范围加以。常用于循环语句的循环次数、常量、数学函数或模式仿真
●Natural:自然数类型,整型的子类型,含零和正整数
●Positive:正整数类型,整型的子类型,含非零和非负整数
●REAL:浮点类型,范围为:-1.0E38到1.0E38很多综合器不支持该类型,仅能在仿真器中使用。
●枚举类型:用户定义的数据类型
例: TYPE traffic_light IS (red, yellow,green )
TYPE int IS RANGE 0 TO 100
signal a : traffic_light ;
●数组类型:分一维数组和二维数组,限定性和非限定性数组
例:
TYPE Bit_Vector IS ARRAY (Natural RANGE<>) OF Bit;
TYPE Word IS ARRARY (31 downto 0) OF Bit;
●SUBTYPE:子类型,一般用来对其父类型加以
例: SUBTYPE Std_Logic IS resolved Std_Ulogic
●TIME:时间类型,范围和整型一样,表达时要包括数值和单位两部分。单位包括:fs、ps、ns、us、ms、sec、min、hr。一般用于仿真,对于逻辑综合来说意义不大。
●记录类型
TYPE Month_Name IS (Jan,Fab,Mar,Apr,May,Jun,Jul,Aug,Sep,Oct,Nov,Dec);
TYPE date IS RECORD
day : Integer RANGE 1 TO 31;
month : Month_Name;
year : Integer RANGE 0 to 3000;
END RECORD;
VARIABLE today : date;
today : =(15, may, 1995);
构造体:
一个实体(ENTITY)可以有多个构造体。构造体的运行是并发的
信号和变量的作用范围:
信号和变量的区别:
运算符:
几种特殊语句结构:
1. With_Select_Then选择信号语句
WITH selection_signal SELECT
signal_name <= value_1 WHEN value_a,
value_2 WHEN value_b,
...
value_n WHEN value_n,
value_x WHEN OTHERS;
说明:所有的“WHEN”子句必须是互斥的
一般用 “When Others”来处理未考虑到的情况
只有一个参考信号和赋值符 (<=)
每一子句结尾是逗号,最后一句是分号
例:WITH s SELECT
x <= a WHEN ”000” | “001” | “010”,
b WHEN "101" | "111
c WHEN OTHERS;
2. When_Else选择信号语句
signal_name <= value_1 WHEN condition1 ELSE
value_2 WHEN condition2 ELSE
...
value_n WHEN conditionn ELSE
value_x;
例:x <= a when (s = “00”) else
b when (s = “01”) else
c when (s = “10”) else
d ;
进程语句
[进程标号:] PROCESS [(信号敏感表)] IS
〈说明区〉
BEGIN
〈顺序语句〉
END PROCESS [进程标号];
相关实例:
1.多路选择器:
Library ieee;
use ieee.std_logic_11.all;
entity simp2_33_34 is
port(a,b,c,d:in std_logic;
s:in std_logic_vector(1 downto 0);
x:out std_logic);
end simp2_33_34;
architecture logic of simp2_33_34 is
begin
with s select
x<=a when "00
b when "01
c when "10
d when others;
end;
、、、、、、、、、、、、、、、、、、、、、、、、、、、、、、、、、、、、、、、、、、、、、、、、
library ieee;
use ieee.std_logic_11.all;
entity if_case_33_34 is port
(a,b,c,d,clk:in std_logic;
sel:in std_logic_vector(1 downto 0 );
y,z:out std_logic);
end if_case_33_34;
architecture logic of if_case_33_34 is
begin
if_label:process(a,b,c,d,sel)
begin
if sel="00"then y<=a;
elsif sel="01"then y<=b;
elsif sel="10"then y<=c;
else y<=d;
end if;
end process if_label;
case_label:
process(a,b,c,d,sel,clk)
begin
case sel is
when "00"=>z<=a;
when "01"=>z<=b;
when "10"=>z<=c;
when "11"=>z<=d;
when others =>z<='0';
end case;
end process case_label;
end logic;
2.两次的输入的4位数据转为8位数据输出
LIBRARY ieee;
USE ieee.std_logic_11.all;
USE ieee.std_logic_unsigned.all;
ENTITY shift4_33_34 IS
PORT ( shft_lft : in std_logic;
d_in : in std_logic_vector(3 downto 0);
q_out : out std_logic_vector(7 downto 0));
END shift4_33_34;
ARCHITECTURE logic OF shift4_33_34 IS
BEGIN
PROCESS(d_in, shft_lft)
VARIABLE shft_var : std_logic_vector(7 DOWNTO 0);
BEGIN
shft_var(7 downto 4) := "0000";--高位
shft_var(3 downto 0) := d_in; --低位
IF shft_lft = '1' THEN
FOR i IN 7 DOWNTO 4 LOOP
shft_var(i) := shft_var(i-4);
END LOOP;
shft_var(3 downto 0) := "0000";
ELSE shft_var := shft_var;
END IF;
q_out <= shft_var;
END PROCESS;
END logic;
3.双向口程序举例:
library ieee;
use ieee.std_logic_11.all;
use ieee.std_logic_unsigned.all;
ENTITY shuangxiangkou_33_34 IS
PORT (clk, ld, oe: IN std_logic;
count: INOUT std_logic_vector(7 DOWNTO 0));
END shuangxiangkou_33_34;
ARCHITECTURE archldcnt OF shuangxiangkou_33_34 IS
SIGNAL int_count: std_logic_vector(7 DOWNTO 0);
BEGIN
cnt: PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
IF ld='1' THEN int_count <= count;
ELSE int_count <= int_count + 1;
END IF;
END IF;
END PROCESS cnt ;
outen: PROCESS (oe, int_count) BEGIN
IF oe = '1' THEN count <= int_count ;
ELSE count <= (OTHERS => 'Z') ;
END IF ;
END PROCESS outen;
END archldcnt;
4..交通灯(4个按键,分别控制交替闪烁的灯信号停在哪里)
LIBRARY ieee;
USE ieee.std_logic_11.ALL;
ENTITY jiaotongdeng IS
PORT ( clock, reset: IN std_logic;
timer1, timer2, timer3,timer4: IN std_logic;--timer1~4接按键
r, y, g,f: OUT std_logic);
END jiaotongdeng;
ARCHITECTURE arch_1 OF jiaotongdeng IS
TYPE traffic_states IS (red, yellow, green,light);
SIGNAL sm : traffic_states;
BEGIN
fsm: PROCESS (clock, reset)
BEGIN
IF reset = '1' THEN sm <= red;
ELSIF rising_edge(clock) THEN
CASE sm IS
WHEN red => IF timer1='1' THEN sm <= green;
END IF;
WHEN green => IF timer2='1' THEN sm <= yellow;
END IF;
WHEN yellow => IF timer3='1' THEN sm <= light;
END IF;
WHEN light=> IF timer4='1' THEN sm <= red;
END IF;
WHEN others => sm <= light;
END CASE;
END IF;
END PROCESS fsm;
r <= '1' WHEN (sm = red) ELSE '0';
g <= '1' WHEN (sm = green) ELSE '0';
y <= '1' WHEN (sm = yellow ) ELSE '0';
f <= '1' WHEN (sm = light ) ELSE '0';
END arch_1;
5.简易数字时钟设计
模块一:60进制计数器
library ieee;
use ieee.std_logic_11.all;
use ieee.std_logic_unsigned.all;
entity liushijinzhi_33_34 is
port( clk,clr,en : in std_logic;
carry :out std_logic;
ge :out std_logic_vector( 3 downto 0);
shi :out std_logic_vector( 3 downto 0));
end ;
architecture one of liushijinzhi_33_34 is
signal g,s :std_logic_vector(3 downto 0);
begin
process(clk,clr,en,g,s)
begin
if clr='1'then
g<="0000"; s<="0000";
elsif clk'event and clk='1' then
if en='0' then
if g="1001" and s="0101" then
g<="0000"; s<="0000";carry<='1';
elsif g="1001" then
g<="0000";s<=s+1;
else
g<=g+1;carry<='0';
end if;
end if;
end if;
end process;
ge<=g;shi<=s;
end;
模块二:24进制计数器
library ieee;
use ieee.std_logic_11.all;
use ieee.std_logic_unsigned.all;
entity ershisi_33_34 is
port(clk,clr,en:in std_logic;
carry :out std_logic;
ge :out std_logic_vector( 3 downto 0);
shi :out std_logic_vector( 3 downto 0));
end ;
architecture one of ershisi_33_34 is
signal g,s :std_logic_vector(3 downto 0);
begin
process(clk,clr,en,g,s)
begin
if clr='1'then
g<="0000"; s<="0000";
elsif clk'event and clk='1' then
if en='0' then
if g="0011" and s="0010" then
g<="0000"; s<="0000";carry<='1';
elsif g="1001" then
g<="0000";s<=s+1;
else
g<=g+1;carry<='0';
end if;
end if;
end if;
end process;
ge<=g;shi<=s;
end;
模块三:蜂鸣器
library ieee;
use ieee.std_logic_11.all;
use ieee.std_logic_unsigned.all;
entity fmq is
port( clk2,clk3 :in std_logic;
mg,ms,fg,fs :in std_logic_vector(3 downto 0);
speaker :out std_logic);
end ;
architecture one of fmq is
begin
process(clk2,clk3,mg,ms,fg,fs)
begin
if (fs=5 and fg=9) and (ms=5 and mg>=5) then
speaker<=clk2;
elsif (fs=0 and fg=0) and (ms=0 and mg=0) then
speaker<=clk3;
else
speaker<='0';
end if;
end process;
end;
模块四:简单的6分频器
library ieee;
use ieee.std_logic_11.all;
use ieee.std_logic_unsigned.all;
entity fpq33_34 is
port( clk :in std_logic;
count :out std_logic);
end;
architecture one of fpq33_34 is
signal m:std_logic_vector(3 downto 0);
begin
process(clk,m)
begin
if clk'event and clk='1' then
if m="0101" then
m<="0000";
count<='1';
else
m<=m+1;
count<='0';
end if;
end if;
end process;
end;
初步实现时钟后的系统总图: