JMB321C_datasheet_1V1_20130902

JMB321\n2. Compliance, Features & Application\n2.1 Compliance\n• • • • Compliant with Serial ATA Port Multiplier Spec. Revision 1.2 Compliant with Serial ATA Port Selector Spec. Revision 1.0 Compliant with Serial ATA PHY Electrical Spec. Revision 1.0 Compliant with Serial ATA High Speed Serialized AT Attachment Spec. Revision 3.1\n\n2.2 General\n• • • • • • • Integrated 6-port SATA II PHY Integrated PLL for SATA II interface Total six independent SATA channel Integrated uP, PROM and SRAM for firmware programming 1.2V core and 3.3V I/O power supply Available in -pin QFN The external Flash memory is mandatory for all applications\n\n2.3 SATA\n• • • • • • • • • • • • • • • Supports 6-port 3.0Gbps SATA II interface Output swing control and automatic impedance calibration for SATA II PHY Supports asynchronous signal recovery Supports spread spectrum clocking Supports partial / slumber power saving mode Automatically speed negotiation Supports BIST and loopback mode Supports staggered spin-up (Optional) Supports Hot-Plug Supports asynchronous notification Supports ATAPI drives Supports command-based and FIS-based switching Supports PM aware and non-PM aware host Supports cascaded mode Supports executing host loaded firmware code\n\n2.4 GPIO\n• Supports 15 GPIOs • Supports SPI interface\n\nCopyright © 2013 JMicron Inc. All rights reserved. Data Sheet Revision 1.1\n\nPage 7\n\nNDA Required 2013/09/02\n\n\r\n

JMB321\n3. Functional Description\nJMB321 integrates six high-speed Serial I/O’s, six SATA upper layers, a microprocessor, and other control logic into the chip. JMB321 can work as an 1 to 5-ports Port Multiplier or 5 to 1-port Port Selector with internal embedded firmware without extra external flash needed. But it also can use external flash interface and with proper firmware programming to extend its capability.\n\n3.1 Block Diagram\nFigure 3.1 Function View of JMB321\nData Bus\n\nSATA HDD\n\nSATA 3Gb/Sec PHY\n\nSATA Upper Layer\n\nClock Gen\n\nReset Circuit SATA HDD SATA 3Gb/Sec PHY SATA Upper Layer\n\nGPIO Circuit\n\nSATA HDD\n\nSATA 3Gb/Sec PHY\n\nSATA Upper Layer\n\nFIS Processor\n\nSATA Upper Layer\n\nSATA 3Gb/Sec PHY\n\nHOST BUS ADAPTER\n\nSATA HDD\n\nSATA 3Gb/Sec PHY\n\nSATA Upper Layer\n\nuP\n\nPROM\n\nSATA HDD\n\nSATA 3Gb/Sec PHY\n\nSATA Upper Layer\n\nSRAM\n\nSPI\n\nPort Multiplier\n\nRegister Bus\n\nCopyright © 2013 JMicron Inc. All rights reserved. Data Sheet Revision 1.1\n\nPage 8\n\nNDA Required 2013/09/02\n\n\r\n

JMB321\n3.2 Operating Mode 3.2.1 Normal Mode\nWhen the pin XTSTN is tied to “high”, JMB321 works in normal mode. After power on sequence and reset operation, uP executes the programs stored in PROM. PROM program initializes settings of this chip and then, thru SPI bus, starts to load the external program and stores it in SRAM if the external flash is available and valid. If the external program is loaded successfully, it will be executed by uP. Generally, the external firmware is customized program to fulfill various applications. If JMB321 fails to load the external program, JMB321 works as a standard 1 to 5-ports Port Multiplier.\n\n3.2.2 Test Mode\nWhen the pin XTSTN is tied to “low”, JMB321 works in test mode.\n\n3.3 Clock\nThe clock source of JMB321 is from AXIN pin. Clock rate is 25MHz. The internal PLL uses this 25MHz clock to generate various clock frequencies for different internal logic blocks of JMB321.\n\n3.4 Reset\nThere are 2-level reset mechanisms in JMB321, i.e. Chip Reset and Protocol Reset.\n\n3.4.1 Chip Reset\nJMB321 uses XRSTN pin and internal Power-On Reset (POR) for Chip Reset. Chip Reset will initialize entire chip and make all circuit at default state. The micro processor will also restart to execute program from default entry point.\n\n3.4.2 Protocol Reset\nProtocol Reset is from host SATA OOB signal. It is used to reset SATA relative operation. The behavior of Protocol Reset is controlled by firmware code.\n\n3.5 Data Bus\nThe bandwidth of JMB321 internal data bus is 600MB/sec. This high speed bus is enough to support all of the Port Multiplier or Port Selector operations.\n\n3.6 Register Bus\nThrough Register Bus, uP controls and monitors all of the logic components in JMB321.\n\nCopyright © 2013 JMicron Inc. All rights reserved. Data Sheet Revision 1.1\n\nPage 9\n\nNDA Required 2013/09/02\n\n\r\n

JMB321\n3.7 Micro Processor\nMicro processor and related data processing circuit mainly will be in charge of . data movement . data comparison . accumulate adding . random number generation Besides, several built-in timers will also help firmware control timing sequence and program flow.\n\n3.8 FIS Processor\nFIS (Frame Information Structure) processor helps micro processor communicate with SATA FIS protocol. The FIS Processor interprets the incoming SATA FIS and generates the outgoing SATA FIS for micro processor.\n\n3.9 SATA Port\nJMB321 is compliant with Serial ATA High Speed Serialized AT Attachment Spec. Revision 3.1. Each SATA port could be configured to be host mode (to connect to HDD) or to be device mode (to controller). Generally, users will just configure only one port to be device mode with other ports in host mode. When a SATA port works under multiplier condition, SATA FIS will be transferred straight between host port and device port, without thru microprocessor. Built-in-self-test (BIST) circuit is implemented in each SATA port. Thru microprocessor, each SATA port will be able to enter testing condition or to generate relevant testing patterns.\n\nCopyright © 2013 JMicron Inc. All rights reserved. Data Sheet Revision 1.1\n\nPage 10\n\nNDA Required 2013/09/02\n\n\r\n

JMB321\n3.10 Port Multiplier Mode\nA Port Multiplier is a mechanism for one active host connection to communicate with multiple devices. A Port Multiplier can be thought of as a simple multiplexer where one active host connection is multiplexed to multiple device connections, as shown below.\n\nPort Multiplier can work under PM-aware or Legacy host controller. With PM-aware host controller, the Port Multiplier’s operation is the same regardless of the switching type used by the host, Command-based switching or FIS-based switching. When JMB321 is at this mode, the SATA ports are configured as: Port 0: device port, connect to HDD 0 Port 1: Port 2: Port 3: Port 4: Port 5: device port, connect to HDD 1 device port, connect to HDD 2 device port, connect to HDD 3 device port, connect to HDD 4 host port, connect to Controller\nNDA Required 2013/09/02\n\nCopyright © 2013 JMicron Inc. All rights reserved. Data Sheet Revision 1.1\n\nPage 11\n\n\r\n

JMB321\n3.11 Port Selector Mode\nPort Selector is a mechanism that allows five different host ports to connect to the same device in order to create a redundant path to that device. Only one host connection to the device is active at a time. A Port Selector can be thought of as a simple multiplexer as shown below.\n\nJMB321 supports only side-band port selection. The active host port is selected by the first successfully OOB linked SATA channel or by a hardware select line, GPIO pin. JMB321 is a protocol-layer port selector. It doesn’t degrade the SATA electrical signals between each pair of SATA link. When JMB321 is at this mode, the SATA ports are configured as: Port 0: device port, connect to HDD Port 1: Port 2: host port, connect to Controller 0 host port, connect to Controller 1\nNDA Required 2013/09/02\n\nCopyright © 2013 JMicron Inc. All rights reserved. Data Sheet Revision 1.1\n\nPage 12\n\n\r\n

JMB321\nPort 3: Port 4: Port 5: host port, connect to Controller 2 host port, connect to Controller 3 host port, connect to Controller 4\n\n3.12 Cascaded Port Multiplier Mode (Optional for the specific part number)\nJMB321 supports to cascade another JMB321 to extend device number. Due to the restrictions of specification, the maximum device number extendable is 15. The requirements of specification are also maintained under this mode, for example, error propagation. The configuration of cascaded port multiplier may look like below:\n\nCopyright © 2013 JMicron Inc. All rights reserved. Data Sheet Revision 1.1\n\nPage 13\n\nNDA Required 2013/09/02\n\n\r\n

JMB321\n3.13 LED Configuration\nJMB321 external firmware code used below GPIO pins to configure its LED operation mode. Setting 1: 1LED for 1 SATA Port as below: GPIO00 GPIO02 GPIO04 GPIO01 GPIO03 GPIO05 SATA Port 0 Ready & Busy SATA Port 1 Ready & Busy SATA Port 2 Ready & Busy SATA Port 3 Ready & Busy SATA Port 4 Ready & Busy SATA Port 5 Ready & Busy\n\nSetting 2: 2LED for 1 SATA Port as below: GPIO00 GPIO01 GPIO02 GPIO03 GPIO04 GPIO05 GPIO06 GPIO07 GPIO08 GPIO09 GPIO10 GPIO11 SATA Port 0 Ready SATA Port 0 Busy SATA Port 1 Ready SATA Port 1 Busy SATA Port 2 Ready SATA Port 2 Busy SATA Port 3 Ready SATA Port 3 Busy SATA Port 4 Ready SATA Port 4 Busy SATA Port 5 Ready SATA Port 5 Busy\n\nCopyright © 2013 JMicron Inc. All rights reserved. Data Sheet Revision 1.1\n\nPage 14\n\nNDA Required 2013/09/02\n\n\r\n

JMB321\n4. Electrical Characteristics 4.1 Absolute Maximum Rating\nParameter Digital 3.3V power supply Digital 1.2V power supply Analog 3.3V power supply Analog 1.2V power supply Digital I/O input voltage Storage Temperature Symbol DV33(ABS) DV12(ABS) AV33X(ABS) AV12X(ABS) VI(D) TSTORAGE Condition Min -0.3 -0.3 -0.3 -0.3 -0.3 -40 Max 3.63 1.32 3.63 1.32 3.63 130 Unit V V V V V\no\n\nC\n\n4.2 Recommended Power Supply Operation Conditions\nParameter Digital 3.3V power supply Digital 1.2V power supply Analog 3.3V power supply Analog 1.2V power supply Ambient operation temperature Junction Temperature Symbol DV33 DV12 AV33X AV12X TA TJ Condition Min 3.14 1.14 3.14 1.14 0 Typical 3.3 1.2 3.3 1.2 Max 3.47 1.26 3.47 1.26 70 125 Unit V V V V\no o\n\nC C\n\n4.3 Recommended External Clock Source Conditions\nParameter External reference clock Clock Duty Cycle 45 Symbol Condition Min Typical 25 50 55 Max Unit MHz %\n\n4.4 Power Supply DC Characteristics\n4.4.1 IDLE\nParameter Digital 3.3V power supply Digital 1.2V power supply Analog 3.3V power supply Analog 1.2V power supply Symbol DV33 DV12 AV33X AV12X Condition Min Typical 19.1 195 81.4 390 Max Unit mA mA mA mA\n\nCopyright © 2013 JMicron Inc. All rights reserved. Data Sheet Revision 1.1\n\nPage 15\n\nNDA Required 2013/09/02\n\n\r\n

JMB321\n4.4.2 Operating\nParameter Digital 3.3V power supply Digital 1.2V power supply Analog 3.3V power supply Analog 1.2V power supply Symbol DV33 DV12 AV33X AV12X Condition Min Typical 35.4 203 81.4 3 Max Unit mA mA mA mA\n\n4.4.3 SUSPEND\nParameter Digital 3.3V power supply Digital 1.2V power supply Analog 3.3V power supply Analog 1.2V power supply Symbol DV33 DV12 AV33X AV12X Condition Min Typical 5.5 113 19.8 129 Max Unit mA mA mA mA\n\n4.5 I/O DC Characteristics\nParameter Input low voltage Input high voltage Output low voltage Output high voltage Symbol VIL VIH VOL VIH 1.9 1.5 0.3 Condition Min Typical Max 0.7 Unit V V V V\n\nCopyright © 2013 JMicron Inc. All rights reserved. Data Sheet Revision 1.1\n\nPage 16\n\nNDA Required 2013/09/02\n\n\r\n

JMB321\n5. Pin Descriptions\nPin Description for all pins described in Section 5 are under normal function. Once other operating modes are selected except Normal mode, all pins have different definition.\n\n5.1 Pin List Table\nTable 5-1 Pin List Table of JMB321\nNo. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name ZGPIO10 ZGPIO09 ZGPIO08 DV12 DGND DV33 ZGPIO07 ZGPIO06 ZGPIO05 ZGPIO04 ZGPIO03 DV33 DGND DV12 ZGPIO02 ZGPIO01 No. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name ZGPIO00 ZGPIO14 ZGPIO13 XTSTN ARXP5 ARXN5 AV125 ATXN5 ATXP5 AV335 ARXP4 ARXN4 AV124 ATXN4 ATXP4 AV334 No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin Name ARXP3 ARXN3 AV123 ATXN3 ATXP3 AV333 AXIN AXOUT AGNDC AREXT AV33C ARXP0 ARXN0 AV120 ATXN0 ATXP0 No. 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Pin Name AV330 ARXP2 ARXN2 AV122 ATXN2 ATXP2 AV332 ARXP1 ARXN1 AV121 ATXN1 ATXP1 AV331 XRSTN ZGPIO12 ZGPIO11\n\nCopyright © 2013 JMicron Inc. All rights reserved. Data Sheet Revision 1.1\n\nPage 17\n\nNDA Required 2013/09/02\n\n\r\n

JMB321\n5.2 Pin Diagram\nFigure 5-1 -Pin QFN\nAGNDC AXOUT\n\nARXN0\n\nAREXT\n\nARXN3\n34 15\n\nARXP0\n\n48\n\n47\n\n46\n\n45\n\n44\n\n43\n\n42\n\n41\n\n40\n\n39\n\n38\n\n37\n\n36\n\n35\n\n10\n\n11\n\n12\n\n13\n\n14\n\nZGPIO10\n\nZGPIO09\n\nZGPIO08\n\nDGND\n\nZGPIO07\n\nZGPIO06\n\nZGPIO05\n\nZGPIO04\n\nZGPIO03\n\nDGND\n\nZGPIO02\n\nA: Analog, D: Digital, I: Input, O: Output, Z: I/O, L: Internal pull-low, H: Internal pull-low, S: Smittch Trigger Input, PWR: Power, GND: Ground\n\nCopyright © 2013 JMicron Inc. All rights reserved. Data Sheet Revision 1.1\n\nZGPIO01\n\nDV12\n\nDV33\n\nDV33\n\nDV12\n\n16\n\n1\n\n2\n\n3\n\n4\n\n5\n\n6\n\n7\n\n8\n\n9\n\n33\n\nARXP3\n\nATXN0\n\nATXN3\n\nAV33C\n\nATXP0\n\nATXP3\n\nAV120\n\nAV333\n\nAV123\n\nAXIN\n\nPage 18\n\nNDA Required 2013/09/02\n\n\r\n