NCP1200-(200D6)

PWM Current-Mode Controller for Low-Power Universal Off-Line Supplies Housed in SOIC−8 or PDIP−8 package, the NCP1200 represents a major leap toward ultra−compact Switchmode Power Supplies. Due to a novel concept, the circuit allows the implementation of a complete offline battery charger or a standby SMPS with few external components. Furthermore, an integrated output short−circuit protection lets the designer build an extremely low−cost AC−DC wall adapter associated with a simplified feedback scheme.

With an internal structure operating at a fixed 40 kHz, 60 kHz or 100 kHz, the controller drives low gate−charge switching devices like an IGBT or a MOSFET thus requiring a very small operating power. Due to current−mode control, the NCP1200 drastically simplifies the

design of reliable and cheap offline converters with extremely low acoustic generation and inherent pulse−by−pulse control.

When the current setpoint falls below a given value, e.g. the output power demand diminishes, the IC automatically enters the skip cycle mode and provides excellent efficiency at light loads. Because this occurs at low peak current, no acoustic noise takes place.

Finally, the IC is self−supplied from the DC rail, eliminating the need of an auxiliary winding. This feature ensures operation in presence of low output voltage or shorts.

Features

•No Auxiliary Winding Operation

•Internal Output Short−Circuit Protection

•Extremely Low No−Load Standby Power

•Current−Mode with Skip−Cycle Capability

•Internal Leading Edge Blanking

•250 mA Peak Current Source/Sink Capability •Internally Fixed Frequency at 40 kHz, 60 kHz and 100 kHz •Direct Optocoupler Connection

•Built−in Frequency Jittering for Lower EMI

•SPICE Models Available for TRANsient and AC Analysis •Internal Temperature Shutdown

•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant

Typical Applications

•AC−DC Adapters

•Offline Battery Chargers

•Auxiliary/Ancillary Power Supplies (USB, Appliances, TVs, etc.)

PDIP−8

P SUFFIX

CASE 626

8

SOIC−8

D SUFFIX

CASE 751

18

5

3

4

(Top View)

Adj

CS

HV

PIN CONNECTIONS

7

6

2NC

FB

GND Drv

V CC

MARKING

DIAGRAMS

See detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet.

ORDERING INFORMATION

xxx= Device Code: 40, 60 or 100

y= Device Code:

4 for 40

6 for 60

1 for 100

A= Assembly Location

L= Wafer Lot

Y, YY= Year

W, WW= Work Week

G, G= Pb−Free Package

1200Pxxx

AWL

YYWWG

1

8

http://onsemi.com

*Please refer to the application information section

Figure 1. Typical Application

PIN FUNCTION DESCRIPTION

Pin No.Pin Name Function Description

1Adj Adjust the Skipping Peak Current This pin lets you adjust the level at which the cycle skipping process takes

place.

2FB Sets the Peak Current Setpoint By connecting an Optocoupler to this pin, the peak current setpoint is adjus-

ted accordingly to the output power demand.

3CS Current Sense Input This pin senses the primary current and routes it to the internal comparator

via an L.E.B.

4GND The IC Ground

5Drv Driving Pulses The driver’s output to an external MOSFET.

6V CC Supplies the IC This pin is connected to an external bulk capacitor of typically 10 m F.

7NC No Connection This un−connected pin ensures adequate creepage distance.

8HV Generates the V CC from the Line Connected to the high−voltage rail, this pin injects a constant current into

the V CC bulk capacitor.

FB

Drv

V CC

NC

HV

Figure 2. Internal Circuit Architecture

MAXIMUM RATINGS

Rating Symbol Value Units Power Supply Voltage

V CC

16

V

Thermal Resistance Junction −to −Air, PDIP −8 version

Thermal Resistance Junction −to −Air, SOIC version Thermal Resistance Junction −to −Case R q JA R q JA R q JC

10017857°C/W

Maximum Junction Temperature Typical Temperature Shutdown T Jmax −

150140

°C Storage Temperature Range

T stg −60 to +150

°C

ESD Capability, HBM Model (All Pins except V CC and HV)− 2.0

kV ESD Capability, Machine Model

−200V Maximum Voltage on Pin 8 (HV), pin 6 (V CC ) Grounded −450V Maximum Voltage on Pin 8 (HV), Pin 6 (V CC ) Decoupled to Ground with 10 m F

−500V Minimum Operating Voltage on Pin 8 (HV)

−

30

V

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

V CC= 11 V unless otherwise noted)

Rating Pin Symbol Min Typ Max Unit DYNAMIC SELF−SUPPLY (All Frequency Versions, Otherwise Noted)

V CC Increasing Level at Which the Current Source Turns−off6V CCOFF10.311.412.5V V CC Decreasing Level at Which the Current Source Turns−on6V CCON8..811V V CC Decreasing Level at Which the Latchoff Phase Ends6V CClatch− 6.3−V Internal IC Consumption, No Output Load on Pin 56I CC1−710880

m A

Note 1

mA Internal IC Consumption, 1 nF Output Load on Pin 5, F SW = 40 kHz6I CC2− 1.2 1.4

Note 2 Internal IC Consumption, 1 nF Output Load on Pin 5, F SW = 60 kHz6I CC2− 1.4 1.6

mA

Note 2

mA Internal IC Consumption, 1 nF Output Load on Pin 5, F SW = 100 kHz6I CC2− 1.9 2.2

Note 2 Internal IC Consumption, Latchoff Phase6I CC3−350−m A INTERNAL CURRENT SOURCE

High−voltage Current Source, V CC = 10 V8I C1 2.8 4.0−mA High−voltage Current Source, V CC = 0 V8I C2− 4.9−mA DRIVE OUTPUT

Output Voltage Rise−time @ CL = 1 nF, 10−90% of Output Signal5T r−67−ns Output Voltage Fall−time @ CL = 1 nF, 10−90% of Output Signal5T f−28−ns Source Resistance (drive = 0, Vgate = V CCHMAX− 1 V)5R OH274061W Sink Resistance (drive = 11 V, Vgate = 1 V)5R OL51225W CURRENT COMPARATOR (Pin 5 Un−loaded)

Input Bias Current @ 1 V Input Level on Pin 33I IB−0.02−m A Maximum internal Current Setpoint3I Limit0.80.9 1.0V Default Internal Current Setpoint for Skip Cycle Operation3I Lskip−350−mV Propagation Delay from Current Detection to Gate OFF State3T DEL−100160ns Leading Edge Blanking Duration3T LEB−230−ns INTERNAL OSCILLATOR (V CC = 11 V, Pin 5 Loaded by 1 k W)

Oscillation Frequency, 40 kHz Version−f OSC3248kHz Oscillation Frequency, 60 kHz Version−f OSC526170kHz Oscillation Frequency, 100 kHz Version−f OSC86103116kHz Built−in Frequency Jittering, F SW = 40 kHz−f jitter−300−Hz/V Built−in Frequency Jittering, F SW = 60 kHz−f jitter−450−Hz/V Built−in Frequency Jittering, F SW = 100 kHz−f jitter−620−Hz/V Maximum Duty Cycle−Dmax748087% FEEDBACK SECTION (V CC = 11 V, Pin 5 Loaded by 1 k W)

Internal Pullup Resistor2Rup−8.0−k W Pin 3 to Current Setpoint Division Ratio−Iratio− 4.0−−SKIP CYCLE GENERATION

Default skip mode level1Vskip 1.1 1.4 1.6V Pin 1 internal output impedance1Zout−25−k W

1.Max value @ T J = −25°C.

2.Max value @ T J = 25°C, please see characterization curves.

2.101.901.501.701.30

1.100.9074628056683886929810411011.5011.3011.6011.2011.4011.70750−25

6075305025L E A K A G E (m A )

0TEMPERATURE (°C)

Figure 3. HV Pin Leakage Current vs.

Temperature

Figure 4. V CC OFF vs. Temperature

V C C O F F (V )

9.859.809.759.709.659.609.559.509.45Figure 5. V CC ON vs. Temperature TEMPERATURE (°C)Figure 6. I CC1 vs. Temperature

TEMPERATURE (°C)

I C C 1 (m A )

V C C O N (V )Figure 7. I CC2 vs. Temperature TEMPERATURE (°C)Figure 8. Switching Frequency vs. T J

TEMPERATURE (°C)

I C C 2 (m A )

F S W (k H z )

650800700600850900TEMPERATURE (°C)1020405010012511.10

05044

1.341.33

1.311.321.301.291.28

76.074.0

78.080.082.084.086.04003404303103701904600.88

−25

6.45125

6.40

25

V C C L A T C H O F F (V )

6.35TEMPERATURE (°C)

Figure 9. V CC Latchoff vs. Temperature Figure 10. I CC3 vs. Temperature

I C C 3 (m A )

60

50403020100Figure 11. DRV Source/Sink Resistances TEMPERATURE (°C)Figure 12. Current Sense Limit vs. Temperature

TEMPERATURE (°C)

C U R R E N T S E T P O I N T (V )

W

Figure 13. V skip vs. Temperature

TEMPERATURE (°C)Figure 14. Max Duty Cycle vs. Temperature

TEMPERATURE (°C)

V s k i p (V )D U T Y −M A X (%)

6.500.920.840.80

0.961.005075250100−25

125

TEMPERATURE (°C)6.206.256.3050

75

100

5075250100−25

1255075250100−25

125

280250220

50

75

25

100

−25

125

APPLICATIONS INFORMATION

INTRODUCTION

The NCP1200 implements a standard current mode architecture where the switch −off time is dictated by the peak current setpoint. This component represents the ideal candidate where low part −count is the key parameter,particularly in low −cost AC −DC adapters, auxiliary supplies etc. Due to its high −performance High −V oltage technology, the NCP1200 incorporates all the necessary components normally needed in UC384X based supplies:timing components, feedback devices, low −pass filter and self −supply . This later point emphasizes the fact that ON Semiconductor’s NCP1200 does NOT need an auxiliary winding to operate: the product is naturally supplied from the high −voltage rail and delivers a V CC to the IC. This system is called the Dynamic Self −Supply (DSS).

Dynamic Self −Supply

The DSS principle is based on the charge/discharge of the V CC bulk capacitor from a low level up to a higher level. We can easily describe the current source operation with a bunch of simple logical equations:

POWER −ON: IF V CC < V CCOFF THEN Current Source is ON, no output pulses

IF V CC decreasing > V CCON THEN Current Source is OFF, output is pulsing

IF V CC increasing < V CCOFF THEN Current Source is ON, output is pulsing

Typical values are: V CCOFF = 11.4 V , V CCON = 9.8 V To better understand the operational principle, Figure 15’s sketch offers the necessary light:

Current Source Figure 15. The Charge/Discharge Cycle

Over a 10 m F V CC Capacitor

V CC

10.6 V Avg.

The DSS behavior actually depends on the internal IC consumption and the MOSFET’s gate charge, Qg. If we select a MOSFET like the MTD1N60E, Qg equals 11 nC (max). With a maximum switching frequency of 48 kHz (for the P40 version), the average power necessary to drive the MOSFET (excluding the driver efficiency and neglecting various voltage drops) is:

Fsw @Qg @V cc

with

Fsw = maximum switching frequency Qg = MOSFET’s gate charge

V CC = V GS level applied to the gate

To obtain the final driver contribution to the IC consumption, simply divide this result by V CC : Idriver =Fsw @Qg = 530 m A. The total standby power consumption at no −load will therefore heavily rely on the internal IC consumption plus the above driving current (altered by the driver’s efficiency). Suppose that the IC is supplied from a 400 V DC line. To fully supply the integrated circuit, let’s imagine the 4 mA source is ON during 8 ms and OFF during 50 ms. The IC power contribution is therefore: 400 V . 4 mA

.

0.16 = 256 mW. If for design reasons this contribution is still too high, several solutions exist to diminish it:1.Use a MOSFET with lower gate charge Qg

2.Connect pin through a diode (1N4007 typically) to one of the mains input. The average value on pin 8

becomes 2*V mains PEAK

p

example drops to: 160 mW.

Figure 16. A simple diode naturally reduces the

average voltage on pin 8

an auxiliary winding. It will automatically

disconnect the internal startup source and the IC

will be fully self−supplied from this winding.

Again, the total power drawn from the mains will

significantly decrease. Make sure the auxiliary

voltage never exceeds the 16 V limit.

Skipping Cycle Mode

The NCP1200 automatically skips switching cycles when the output power demand drops below a given level. This is accomplished by monitoring the FB pin. In normal operation, pin 2 imposes a peak current accordingly to the load value. If the load demand decreases, the internal loop asks for less peak current. When this setpoint reaches a determined level, the IC prevents the current from decreasing further down and starts to blank the output pulses: the IC enters the so−called skip cycle mode, also named controlled burst operation. The power transfer now depends upon the width of the pulse bunches (Figure 18 ). Suppose we have the following component values:

Lp, primary inductance = 1 mH

F SW, switching frequency = 48 kHz

Ip skip = 300 mA (or 350 mV / Rsense)

The theoretical power transfer is therefore:

1

2@Lp@Ip 2@Fsw+2.2W

If this IC enters skip cycle mode with a bunch length of 10 ms over a recurrent period of 100 ms, then the total power transfer is: 2.2 . 0.1 = 220 mW.

To better understand how this skip cycle mode takes place, a look at the operation mode versus the FB level immediately gives the necessary insight:

FB

Figure 17. Feedback Voltage Variations

When FB is above the skip cycle threshold (1.4 V by default), the peak current cannot exceed 1 V/Rsense. When the IC enters the skip cycle mode, the peak current cannot go below Vpin1 / 4 (Figure 19). The user still has the flexibility to alter this 1.4 V by either shunting pin 1 to ground through a resistor or raising it through a resistor up to the desired level.

Figure 18. Output pulses at various power levels

(X = 5 m s/div) P1P1

P2

P3

Figure 19. The skip cycle takes place at low peak

currents which guarantees noise free operation

Max Peak

Current

Skip Cycle

Current LimitPower Dissipation

The NCP1200 is directly supplied from the DC rail through the internal DSS circuitry. The current flowing through the DSS is therefore the direct image of the NCP1200 current consumption. The total power dissipation

can be evaluated using: (V

HVDC *11V)@ICC2. If we

operate the device on a 250 V AC rail, the maximum rectified voltage can go up to 350 VDC. As a result, the worse case dissipation occurs on the 100 kHz version which will dissipate 340 . 1.8 mA@Tj = −25°C = 612 mW (however this 1.8 mA number will drop at higher operating temperatures). Please note that in the above example, I CC2 is based on a 1 nF capacitor loading pin 5. As seen before, I CC2 will depend on your MOSFET’s Q g: I CC2 = I CC1 + F sw x Q g. Final calculations shall thus account for the total gate−charge Q g your MOSFET will exhibit. A DIP8 package offers a junction−to−ambient thermal resistance of R q J−A100°C/W. The maximum power dissipation can thus be computed knowing the maximum operating ambient temperature (e.g. 70°C) together with the maximum allowable junction temperature (125°C):

Pmax+T Jmax*T Amax

R R q J*A

= 550 mW. As we can see, we do not

reach the worse consumption budget imposed by the 100 kHz version. Two solutions exist to cure this trouble. The first one consists in adding some copper area around the NCP1200 DIP8 footprint. By adding a min−pad area of 80 mm2 of 35 m copper (1 oz.) R q J−A drops to about 75°C/W which allows the use of the 100 kHz version. The other solutions are:

1.Add a series diode with pin 8 (as suggested in the

above lines) to drop the maximum input voltage

down to 222 V ((2 350)/pi) and thus dissipate

less than 400 mW

2.Implement a self−supply through an auxiliary

winding to permanently disconnect the self−supply. SOIC−8 package offers a worse R q J−A compared to that of the DIP8 package: 178°C/W. Again, adding some copper area around the PCB footprint will help decrease this number: 12 mm x 12 mm to drop R q J−A down to 100°C/W with 35 m copper thickness (1 oz.) or 6.5 mm x 6.5 mm with 70 m copper thickness (2 oz.). One can see, we do not recommend using the SOIC package for the 100 kHz version with DSS active as the IC may not be able to sustain the power (except if you have the adequate place on your PCB). However, using the solution of the series diode or the self−supply through the auxiliary winding does not cause any problem with this frequency version. These options are thoroughly described in the AND8023/D.Overload Operation

In applications where the output current is purposely not controlled (e.g. wall adapters delivering raw DC level), it is interesting to implement a true short−circuit protection. A short−circuit actually forces the output voltage to be at a low level, preventing a bias current to circulate in the optocoupler LED. As a result, the FB pin level is pulled up to 4.1 V, as internally imposed by the IC. The peak current setpoint goes to the maximum and the supply delivers a rather high power with all the associated effects. Please note that this can also happen in case of feedback loss, e.g. a broken optocoupler. To account for this situation, the NCP1200 hosts a dedicated overload detection circuitry. Once activated, this circuitry imposes to deliver pulses in a burst manner with a low duty cycle. The system recovers when the fault condition disappears.

During the startup phase, the peak current is pushed to the maximum until the output voltage reaches its target and the feedback loop takes over. This period of time depends on normal output load conditions and the maximum peak current allowed by the system. The time−out used by this IC works with the V CC decoupling capacitor: as soon as the V CC decreases from the V CCOFF level (typically 11.4 V) the device internally watches for an overload current situation. If this condition is still present when V CCON is reached, the controller stops the driving pulses, prevents the self−supply current source to restart and puts all the circuitry in standby, consuming as little as 350 m A typical (I CC3 parameter). As a result, the V CC level slowly discharges toward 0. When this level crosses 6.3 V typical, the controller enters a new startup phase by turning the current source on: V CC rises toward 11.4 V and again delivers output pulses at the UVLO H crossing point. If the fault condition has been removed before UVLO L approaches, then the IC continues its normal operation. Otherwise, a new fault cycle takes place. Figure 20 shows the evolution of the signals in presence of a fault.

Time

Time

Time

V 11.4 V 9.8 V 6.3 V

Figure 20. If the fault is relaxed during the V CC natural fall down sequence, the IC automatically resumes.If the fault persists when V CC reached UVLO L , then the controller cuts everything off until recovery.

Calculating the V CC Capacitor

As the above section describes, the fall down sequence depends upon the V CC level: how long does it take for the V CC line to go from 11.4 V to 9.8 V? The required time depends on the startup sequence of your system, i.e. when you first apply the power to the IC. The corresponding transient fault duration due to the output capacitor charging must be less than the time needed to discharge from 11.4 V to 9.8 V , otherwise the supply will not properly start. The test consists in either simulating or measuring in the lab how much time the system takes to reach the regulation at full load. Let’s suppose that this time corresponds to 6ms.Therefore a V CC fall time of 10 ms could be well appropriated in order to not trigger the overload detection circuitry. If the corresponding IC consumption, including the MOSFET drive, establishes at 1.5 mA, we can calculate the required capacitor using the following formula:D t +D V @C i

, with D V = 2V . Then for a wanted D t of 10 ms,

C equals 8 m F or 10 m F for a standard value. When an overload condition occurs, the IC blocks its internal circuitry and its consumption drops to 350 m A typical. This appends at V CC = 9.8 V and it remains stuck until V CC reaches 6.5 V: we are in latchoff phase. Again, using the calculated 10 m F and 350 m A current consumption, this latchoff phase lasts: 109 ms.

Protecting the Controller Against Negative Spikes As with any controller built upon a CMOS technology, it is the designer’s duty to avoid the presence of negative spikes on sensitive pins. Negative signals have the bad habit to forward bias the controller substrate and induce erratic behaviors. Sometimes, the injection can be so strong that internal parasitic SCRs are triggered, engendering irremediable damages to the IC if they are a low impedance path is offered between V CC and GND. If the current sense pin is often the seat of such spurious signals, the high −voltage pin can also be the source of problems in certain circumstances. During the turn −off sequence, e.g.when the user unplugs the power supply, the controller is still fed by its V CC capacitor and keeps activating the MOSFET ON and OFF with a peak current limited by Rsense.Unfortunately, if the quality coefficient Q of the resonating network formed by Lp and Cbulk is low (e.g. the MOSFET Rdson + Rsense are small), conditions are met to make the circuit resonate and thus negatively bias the controller. Since we are talking about ms pulses, the amount of injected charge (Q = I x t) immediately latches the controller which brutally discharges its V CC capacitor. If this V CC capacitor is of sufficient value, its stored energy damages the controller. Figure 21 depicts a typical negative shot occurring on the HV pin where the brutal V CC discharge testifies for latchup.

Figure 21. A negative spike takes place on the Bulk capacitor at the switch −off sequence

Simple and inexpensive cures exist to prevent from internal parasitic SCR activation. One of them consists in inserting a resistor in series with the high −voltage pin to keep the negative current to the lowest when the bulk becomes negative (Figure 22). Please note that the negative spike is clamped to –2 x Vf due to the diode bridge. Please refer to AND8069/D for power dissipation calculations.

Another option (Figure 23) consists in wiring a diode from V CC to the bulk capacitor to force V CC to reach UVLOlow sooner and thus stops the switching activity before the bulk capacitor gets deeply discharged. For security reasons, two diodes can be connected in series.

Figure 22. A simple resistor in series avoids any

latchup in the controller CV CC

D3

1N4007

CV CC

Rbulk > 4.7 k

Figure 23. or a diode forces V CC to reach

UVLOlow sooner

A Typical Application

Figure 24 depicts a low −cost 3.5 W AC −DC 6.5 V wall adapter. This is a typical application where the wall −pack must deliver a raw DC level to a given internally regulated apparatus: toys, calculators, CD players etc. Due to the

inherent short −circuit protection of the NCP1200, you only need a bunch of components around the IC, keeping the final cost at an extremely low level. The transformer is available from different suppliers as detailed on the following page.

Figure 24. A typical AC−DC wall adapter showing the reduced part count due to the NCP1200

T1: Lp = 2.9 mH, Np:Ns = 1:0.08, leakage = 80 m H, E16 core, NCP1200P40

To help designers during the design stage, several manufacturers propose ready−to−use transformers for the above application, but can also develop devices based on your particular specification:

Eldor Corporation Headquarter

Via Plinio 10,

22030 Orsenigo

(Como) Italia

Tel.: +39−031−636 111

Fax : +39−031−636 280

Email: eldor@eldor.it

www.eldor.it

ref. 1: 2262.0058C: 3.5 W version

(Lp = 2.9 mH, Lleak = 80 m H, E16)

ref. 2: 2262.0059A: 5 W version

(Lp = 1.6 mH, Lleak = 45 m H, E16) Atelier Special de Bobinage

125 cours Jean Jaures

38130 ECHIROLLES FRANCE

Tel.: 33 (0)4 76 23 02 24

Fax: 33 (0)4 76 22

Email: asb@wanadoo.fr

ref. 1: NCP1200−10 W−UM: 10 W for USB (Lp = 1.8 mH, 60 kHz, 1:0.1, RM8 pot core)Coilcraft

1102 Silver Lake Road

Cary, Illinois 60013 USA

Tel: (847) 639−00

Fax: (847) 639−1469

Email: info@coilcraft.com

http://www.coilcraft.com

ref. 1: Y8844−A: 3.5 W version

(Lp = 2.9 mH, Lleak = 65 m H, E16)

ref. 2: Y8848−A: 10 W version

(Lp = 1.8 mH, Lleak = 45 m H, 1:01, E core)

Improving the Output Drive Capability

The NCP1200 features an asymmetrical output stage used to soften the EMI signature. Figure 25 depicts the way the driver is internally made:

V

Q\

Figure 25. The higher ON resistor slows down

the MOSFET while the lower OFF resistor

ensures fast turn−off.

In some cases, it is possible to expand the output drive capability by adding either one or two bipolar transistors. Figures 26, 27, and 28 give solutions whether you need to improve the turn−on time only, the turn−off time or both. Rd is there to damp any overshoot resulting from long copper traces. It can be omitted with short connections. Results showed a rise fall time improvement by 5X with standard 2N2222/2N2907:

To Gate Figure 26. Improving Both Turn−On and

Turn−

Off Times

To Gate Figure 27. Improving Turn−Off Time Only

To Gate Figure 28. Improving Turn−On Time OnlyIf the leakage inductance is kept low, the MTD1N60E can withstand accidental avalanche energy, e.g. during a high−voltage spike superimposed over the mains, without the help of a clamping network. If this leakage path permanently forces a drain−source voltage above the MOSFET BVdss (600 V), a clamping network is mandatory and must be built around Rclamp and Clamp. Dclamp shall react extremely fast and can be a MUR160 type. To calculate the component values, the following formulas will help you: R clamp=

2@V clamp@(V clamp*(V out)Vf sec)@N)

L leak@Ip2@Fsw

C clamp+

V clamp

V ripple@Fsw@R clamp

with:

V clamp: the desired clamping level, must be selected to be between 40 V to 80 V above the reflected output voltage when the supply is heavily loaded.

V out + Vf: the regulated output voltage level + the secondary diode voltage drop

L leak: the primary leakage inductance

N: the Ns:Np conversion ratio

F SW: the switching frequency V ripple: the clamping ripple, could be around 20 V Another option lies in implementing a snubber network which will damp the leakage oscillations but also provide more capacitance at the MOSFET’s turn−off. The peak voltage at which the leakage forces the drain is calculated by:

V max+Ip@

L leak

C lump

Ǹ

where C lump represents the total parasitic capacitance seen at the MOSFET opening. Typical values for Rsnubber and Csnubber in this 4W application could respectively be 1.5 k W and 47 pF. Further tweaking is nevertheless necessary to tune the dissipated power versus standby power. Available Documents

“Implementing the NCP1200 in Low−cost AC−DC Converters”, AND8023/D.

“Conducted EMI Filter Design for the NCP1200’’, AND8032/D.

“Ramp Compensation for the NCP1200’’, AND8029/D. TRANSient and AC models available to download at: http://onsemi.com/pub/NCP1200

NCP1200 design spreadsheet available to download at: http://onsemi.com/pub/NCP1200

ORDERING INFORMATION

Device Type Marking Package Shipping†

NCP1200P40G

F SW = 40 kHz 1200P40PDIP−8

(Pb−Free)

50 Units / Rail

NCP1200D40R2G200D4SOIC−8

(Pb−Free)

2500 / Tape & Reel

NCP1200P60G

F SW = 60 kHz 1200P60PDIP−8

(Pb−Free)

50 Units / Rail

NCP1200D60R2G200D6SOIC−8

(Pb−Free)

2500 / Tape & Reel

NCP1200P100G

F SW = 100 kHz 1200P100PDIP−8

(Pb−Free)

50 Units / Rail

NCP1200D100R2G200D1SOIC−8

(Pb−Free)

2500 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

PDIP −8P SUFFIX CASE 626−05ISSUE L

NOTES:

1.DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.

2.PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS).

3.DIMENSIONING AND TOLERANCING PER ANSI Y1

4.5M, 1982.

DIM MIN MAX MIN MAX INCHES

MILLIMETERS A 9.4010.160.3700.400B 6.10 6.600.2400.260C 3.94 4.450.1550.175D 0.380.510.0150.020F 1.02 1.780.0400.070G 2.54 BSC 0.100 BSC H 0.76 1.270.0300.050J 0.200.300.0080.012K 2.92 3.430.1150.135L 7.62 BSC 0.300 BSC M ---10 ---10 N

0.76 1.01

0.0300.040

__

SOIC −8 NB CASE 751−07ISSUE AJ

NOTES:

1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 198

2.

2.CONTROLLING DIMENSION: MILLIMETER.

3.DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.

4.MAXIMUM MOLD PROTRUSION 0.15 (0.006)PER SIDE.

5.DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

6.751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−0

7.

DIM A MIN MAX MIN MAX INCHES

4.80

5.000.10.197MILLIMETERS B 3.80 4.000.1500.157C 1.35 1.750.0530.069D 0.330.510.0130.020G 1.27 BSC 0.050 BSC H 0.100.250.0040.010J 0.190.250.0070.010K 0.40 1.270.0160.050M 0 8 0 8 N 0.250.500.0100.020S

5.80

6.20

0.2280.244

M

Y

M

0.25 (0.010)

Y

M

0.25 (0.010)

Z S

X

S

____0.60.024ǒmm inches

ǓSCALE 6:1

*For additional information on our Pb −Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

The product described herein (NCP1200), may be covered by the following U.S. patents: 6,271,735, 6,362,067, 6,385,060, 6,429,709, 6,587,357. There may be other patents pending.