Verilog HDL洗衣机控制器

mod 切换模式，一共有停机s0,调整时间s1，漂洗s2，洗涤s3，脱水s4，共五种状态

add 为调整时间累加,最后赋给timecount

piaocount 是漂洗计数

xicount是洗涤计数

tuocount是脱水计数

zheng表示电机正转

fan表示电机反转

module wash(mod,add,led1,led2,led3,led4,clk,zheng,fan);

input mod,add,clk;

output led1,led2,led3,led4,zheng,fan;

reg led1,led2,led3,led4;

reg zheng,fan;

reg [9:0] timecount,counter;

reg [4:0] piaocount,xicount,tuocount;

reg [2:0] state;

parameter s0=3'b000;

parameter s1=3'b001;

parameter s2=3'b010;

parameter s3=3'b011;

parameter s4=3'b100;

always @(posedge add)

      begin

if(counter<600)

counter<=counter+10'd60;

        else

counter<=0;

      end 

always @(posedge clk)

begin

   begin 

zheng<=0;

fan<=0;

   end 

   case(state)

     s0:

        begin

zheng<=0;fan<=0;

timecount<=0;

led1<=1'b0;

led2<=1'b0;

led3<=1'b0;

led4<=1'b0;

piaocount<=5'b00000;

xicount<=5'b00000;

tuocount<=5'b00000;

          if(mod)

state<=s1;

          else 

state<=s0;

        end

     s1:begin

led1<=1'b1;

led2<=1'b0;

led3<=1'b0;

led4<=1'b0;

           begin

timecount<=counter;

           end

           if(mod)

state<=s2;

           else 

state<=s1;

        end

      s2:begin

led1<=1'b0;

led2<=1'b1;

led3<=1'b0;

led4<=1'b0;

piaocount<=5'b00000;

xicount<=5'b00000;

tuocount<=5'b00000;

               if(mod)

state<=s3;

               else 

state<=s2;

           begin

piaocount<=piaocount+1'b1;

                 if(piaocount==5'b01010)

piaocount<=5'b00000;

else if(piaocount>=5'b00101)

                   begin

zheng<=1'b1;fan<=1'b0;

                   end

                 else

                    begin

zheng<=1'b0;fan<=1'b1;

                    end

            end

         end        

        s3:begin

led1<=1'b0;

led2<=1'b0;

led3<=1'b1;

led4<=1'b0;

piaocount<=5'b00000;

xicount<=5'b00000;

tuocount<=5'b00000;

           if(mod)

state<=s4;

               else 

state<=s3;

            begin

xicount<=xicount+1'b1;

                 if(xicount==5'b10100)

xicount<=5'b00000;

else if(xicount>=5'b01010)

                   begin

zheng<=1'b1;fan<=1'b0;

                   end

                 else

                    begin

zheng<=1'b0;fan<=1'b1;

                    end

            end

           end   

        s4:begin

led1<=1'b0;

led2<=1'b0;

led3<=1'b0;

led4<=1'b1;

piaocount<=5'b00000;

xicount<=5'b00000;

tuocount<=5'b00000;

           if(mod)

state<=s0;

               else 

state<=s4;

           begin

tuocount<=tuocount+1'b1;

                 if(tuocount==5'b00010)

tuocount<=5'b00000;

else if(tuocount>=4'b00001)

                   begin

zheng<=1'b1;fan<=1'b0;

                   end

                 else

                    begin

zheng<=1'b0;fan<=1'b1;

                    end

            end

         end   

        default:

                   begin

state<=s0;

                   end

    endcase

  end

endmodule

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