题目 设计一个自动售货机 成绩
专业 课程名称、代码
年级 姓名
学 号 时间 年 月
设计一个自动售货机
基本要求：可以对3种不同种类的货物进行自动售货,价格分别为A=1.00, B=1.50, C=1.60。售货机可以接受1元,5角,1角三种硬币(即有三种输入信号IY,IWJ,IYJ),并且在7段数码管(二位代表元,一位代表角)显示已投入的总钱数,选择货物的输入信号Ia,Ib,Ic,输出指示信号为 Sa, Sb ,Sc 分别表示售出相应的货物,同时输出的信号yuan, jiao代表找零，并显示在7段数码管上。
规格说明：
1.按一下button1按钮，表示购买货物A，第一个LED灯亮；按两下button1按钮，表示购买货物B，第二个LED灯亮；按三下button1按钮，表示购买货物C，第三个LED灯亮。
2.LED灯亮后，开始输入硬币。button2按一下，输入1元，按两下，输入两元，以此类推；Button3按一下输入5角，按两下代表1元，以此类推；button4按一下输入1角，按两下输入2角，以此类推。7段数码管显示已投入的总钱数，再次按下button1键，7段数码管显示找零数目，同时指示货物的LED灯熄灭。
3.本实验使用FPGA板：Sparant6XC6SLX16CSG324C（建project时，需要选择该芯片的型号）。
论文要求：
1.论文的格式采用标准的深圳大学以论文、报告等形式考核专用答题纸；
2.论文中应完包括ASM图, 以及VerilogHDL代码，并且代码应该与ASM图相一致.
3.论文应包括该电路的VerilogHDL仿真.
4.论文应该有FPGA开发的布局布线后结果.
5.报告应该有实验成功的开发板截图.
1.状态图
本设计需要2个状态机，一个是售货机工作状态机，一个是按键消抖用的FSM
2. Verilog 代码：
`timescale 1ns / 1ps
module automat(clk_in,reset,cs,Led,seg,button1_in,button2_in,button3_in,button4_in
);
input clk_in,reset;
input button1_in,button2_in,button3_in,button4_in;
output [2:0] Led;
output [3:0] cs;
output [7:0] seg;
reg [7:0] seg;
reg [3:0] cs;
reg [2:0] Led;
reg [6:0] total;
reg [4:0] state;
reg [2:0] state1,state2,state3,state4;
reg [4:0] cnt1,cnt2,cnt3,cnt4;
reg button1,button2,button3,button4;
reg [6:0] ones,tens;
reg clk;
reg [23:0] divcnt;
parameter wait0 = 3'b001;
parameter delay = 3'b010;
parameter wait1 = 3'b100;
parameter idle = 5'b00001;
parameter selA = 5'b00010;
parameter selB = 5'b00100;
parameter selC = 5'b01000;
parameter count = 5'b10000;
always @ (posedge clk_in or negedge reset) /// clk_divider
begin
if (!reset)
begin
clk <= 1'b0;
divcnt <= 0;
end
else if (divcnt == 99999)
begin
clk <= 1'b1;
divcnt <= 0;
end
else if (divcnt == 49999)
begin
clk <= 1'b0;
divcnt <= divcnt + 1;
end
else
divcnt <= divcnt + 1;
end
always @ (posedge clk or negedge reset) // 7seg scan clk=1Khz
begin
if (!reset)
begin
cs <= 4'b1101;
seg <= 8'b00111000;
end
else if (cs == 4'b1101)
begin
cs <= 4'b1110;
case(ones)
0: seg <= 8'b10000001;
1: seg <= 8'b11001111;
2: seg <= 8'b10010010;
3: seg <= 8'b10000110;
4: seg <= 8'b11001100;
5: seg <= 8'b10100100;
6: seg <= 8'b10100000;
7: seg <= 8'b10001111;
8: seg <= 8'b10000000;
9: seg <= 8'b10000100;
default: seg <= 8'b01110000;
endcase
end
else if (cs == 4'b1110)
begin
cs <= 4'b1101;
case(tens)
0: seg <= 8'b00000001;
1: seg <= 8'b01001111;
2: seg <= 8'b00010010;
3: seg <= 8'b00000110;
4: seg <= 8'b01001100;
5: seg <= 8'b00100100;
6: seg <= 8'b00100000;
7: seg <= 8'b00001111;
8: seg <= 8'b00000000;
9: seg <= 8'b00000100;
default: seg <= 8'b01110000;
endcase
end
end
always @ (total) //total decode
begin
if (total < 10 && total >= 0)
begin
tens = 0;
ones = total;
end
else if (total < 20 && total >= 10)
begin
tens = 1;
ones = total - 10;
end
else if (total < 30 && total >= 20)
begin
tens = 2;
ones = total - 20;
end
else if (total < 40 && total >= 30)
begin
tens = 3;
ones = total - 30;
end
else if (total < 50 && total >= 40)
begin
tens = 4;
ones = total - 40;
end
else if (total < 60 && total >= 50)
begin
tens = 5;
ones = total - 50;
end
else if (total < 70 && total >= 60)
begin
tens = 6;
ones = total - 60;
end
else if (total < 80 && total >= 70)
begin
tens = 7;
ones = total - 70;
end
else if (total < 90 && total >= 80)
begin
tens = 8;
ones = total - 80;
end
else if (total < 100 && total >= 90)
begin
tens = 9;
ones = total - 90;
end
else
begin
tens = 9;
ones = 9;
end
end
always @ (posedge clk or negedge reset) // undo key jitter fsm for button1_in
begin
if (!reset)
begin
button1 <= 1'b0;
cnt1 <= 0;
state1 <= wait0;
end
else
begin
button1 <= 1'b0;
case (state1)
wait0: begin
if (button1_in)
state1 <= delay;
else
state1 <= wait0;
end
delay: begin
if (cnt1 == 24)
begin
cnt1 <= 0;
if (button1_in)
begin
button1 <= 1'b1;
state1 <= wait1;
end
else
state1 <= wait0;
end
else
begin
cnt1 <= cnt1 + 1;
state1 <= delay;
end
end
wait1: begin
if (button1_in)
state1 <= wait1;
else
state1 <= wait0;
end
default: state1 <= wait0;
endcase
end
end
always @ (posedge clk or negedge reset) // undo key jitter fsm for button2_in
begin
if (!reset)
begin
button2 <= 1'b0;
cnt2 <= 0;
state2 <= wait0;
end
else
begin
button2 <= 1'b0;
case (state2)
wait0: begin
if (button2_in)
state2 <= delay;
else
state2 <= wait0;
end
delay: begin
if (cnt2 == 24)
begin
cnt2 <= 0;
if (button2_in)
begin
button2 <= 1'b1;
state2 <= wait1;
end
else
state2 <= wait0;
end
else
begin
cnt2 <= cnt2 + 1;
state2 <= delay;
end
end
wait1: begin
if (button2_in)
state2 <= wait1;
else
state2 <= wait0;
end
default: state2 <= wait0;
endcase
end
end
always @ (posedge clk or negedge reset) // undo key jitter fsm for button3_in
begin
if (!reset)
begin
button3 <= 1'b0;
cnt3 <= 0;
state3 <= wait0;
end
else
begin
button3 <= 1'b0;
case (state3)
wait0: begin
if (button3_in)
state3 <= delay;
else
state3 <= wait0;
end
delay: begin
if (cnt3 == 24)
begin
cnt3 <= 0;
if (button3_in)
begin
button3 <= 1'b1;
state3 <= wait1;
end
else
state3 <= wait0;
end
else
begin
cnt3 <= cnt3 + 1;
state3 <= delay;
end
end
wait1: begin
if (button3_in)
state3 <= wait1;
else
state3 <= wait0;
end
default: state3 <= wait0;
endcase
end
end
always @ (posedge clk or negedge reset) // undo key jitter fsm for button3_in
begin
if (!reset)
begin
button4 <= 1'b0;
cnt4 <= 0;
state4 <= wait0;
end
else
begin
button4 <= 1'b0;
case (state4)
wait0: begin
if (button4_in)
state4 <= delay;
else
state4 <= wait0;
end
delay: begin
if (cnt4 == 24)
begin
cnt4 <= 0;
if (button4_in)
begin
button4 <= 1'b1;
state4 <= wait1;
end
else
state4 <= wait0;
end
else
begin
cnt4 <= cnt4 + 1;
state4 <= delay;
end
end
wait1: begin
if (button4_in)
state4 <= wait1;
else
state4 <= wait0;
end
default: state4 <= wait0;
endcase
end
end
always @ (posedge clk or negedge reset) //FSM for automat
begin
if (!reset)
begin
total <= 0;
Led <= 3'b000;
state <= idle;
end
else
begin
case (state)
idle: begin
Led <= 3'b000;
if (button1)
state <= selA;
else
state <= idle;
end
selA: begin
total <= 0;
Led <= 3'b100;
if (button1)
state <= selB;
else if (button2)
begin
state <= count;
total <= total + 10;
end
else if (button3)
begin
state <= count;
total <= total + 5;
end
else if (button4)
begin
state <= count;
total <= total + 1;
end
else
state <= selA;
end
selB: begin
Led <= 3'b010;
if (button1)
state <= selC;
else if (button2)
begin
state <= count;
total <= total + 10;
end
else if (button3)
begin
state <= count;
total <= total + 5;
end
else if (button4)
begin
state <= count;
total <= total + 1;
end
else
state <= selB;
end
selC: begin
Led <= 3'b001;
if (button2)
begin
state <= count;
total <= total + 10;
end
else if (button3)
begin
state <= count;
total <= total + 5;
end
else if (button4)
begin
state <= count;
total <= total + 1;
end
else
state <= selC;
end
count: begin
if (button2)
begin
state <= count;
total <= total + 10;
end
else if (button3)
begin
state <= count;
total <= total + 5;
end
else if (button4)
begin
state <= count;
total <= total + 1;
end
else if (button1 && (total >= 10) && Led == 3'b100)
begin
total <= total - 10;
state <= idle;
end
else if (button1 && (total >= 15) && Led == 3'b010)
begin
total <= total - 15;
state <= idle;
end
else if (button1 && (total >= 16) && Led == 3'b001)
begin
total <= total - 16;
state <= idle;
end
else
state <= count;
end
default: state <= idle;
endcase
end
end
endmodule
3.仿真:
Tb代码：
`timescale 1ns / 1ps
module tb;
endmodule
把button1_in 仿真成与物理电路一样 有大约十几秒的抖动
Button1 正确的忽略掉抖动产生的影响，产生了一个周期的脉冲
买A=1元仿真的过程：button1一来state进入买selA状态 button2一来state 进入count状态且total+10 （total=投进钱总数剩10）即表示投进了1元，button3一来 total = 15 表示投进了1.5元,button4一来 total = 16 表示投了1.6元，最后按button1 出货和找零，total=6表示找零0.6角
4.实物展示：
本设计下载平台是 Nexys3™ Board
Ucf：
#clk
Net "clk_in" LOC=V10 | IOSTANDARD=LVCMOS33;
Net "clk_in" TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;
Net "reset" LOC = T10 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L29N_GCLK2, Sch name = SW0
## Leds
Net "Led<0>" LOC = U16 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L2P_CMPCLK, Sch name = LD0
Net "Led<1>" LOC = V16 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L2N_CMPMOSI, Sch name = LD1
Net "Led<2>" LOC = U15 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L5P, Sch name = LD2
#Net "seg<7>" LOC = M13 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L61N, Sch name = DP
## 7 segment display
Net "seg<6>" LOC = T17 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L51P_M1DQ12, Sch name = CA
Net "seg<5>" LOC = T18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L51N_M1DQ13, Sch name = CB
Net "seg<4>" LOC = U17 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L52P_M1DQ14, Sch name = CC
Net "seg<3>" LOC = U18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L52N_M1DQ15, Sch name = CD
Net "seg<2>" LOC = M14 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L53P, Sch name = CE
Net "seg<1>" LOC = N14 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L53N_VREF, Sch name = CF
Net "seg<0>" LOC = L14 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L61P, Sch name = CG
Net "seg<7>" LOC = M13 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L61N, Sch name = DP
Net "cs<0>" LOC = N16 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L50N_M1UDQSN, Sch name = AN0
Net "cs<1>" LOC = N15 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L50P_M1UDQS, Sch name = AN1
Net "cs<2>" LOC = P18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L49N_M1DQ11, Sch name = AN2
Net "cs<3>" LOC = P17 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L49P_M1DQ10, Sch name = AN3
## Buttons
Net "button1_in" LOC = A8 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L33N, Sch name = BTNU
Net "button2_in" LOC = C4 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L1N_VREF, Sch name = BTNL
Net "button3_in" LOC = C9 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L34N_GCLK18, Sch name = BTND
Net "button4_in" LOC = D9 | IOSTANDARD = LVCMOS33; # Bank = 0, pin name = IO_L34P_GCLK19, Sch name = BTNR
实物图：
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