NCP3170

Synchronous PWM Switching Converter

The NCP3170 is a flexible synchronous PWM Switching Buck Regulator. The NCP3170 operates from 4.5 V to 18 V, sourcing up to 3 A and is capable of producing output voltages as low as 0.8 V. The NCP3170 also incorporates current mode control. To reduce the number of external components, a number of features are internally set including soft start, power good detection, and switching frequency. The NCP3170 is currently available in an SOIC−8 package. Features

•4.5 V to 18 V Operating Input V oltage Range

•90 m W High−Side, 25 m W Low−Side Switch

•FMEA Fault Tolerant During Pin Short Test

•3 A Continuous Output Current

•Fixed 500 kHz and 1 MHz PWM Operation

•Cycle−by−Cycle Current Monitoring

•1.5% Initial Output Accuracy

•Internal 4.6 ms Soft−Start

•Short−Circuit Protection

•Turn on Into Pre−bias

•Power Good Indication

•Light Load Efficiency

•Thermal Shutdown

•These are Pb−Free Devices

Typical Applications

•Set Top Boxes

•DVD/ Blu−ray™ Drives and HDD

•LCD Monitors and TVs

•Cable Modems

•PCIe Graphics Cards

•Telecom/Networking/Datacom Equipment

•Point of Load DC/DC Converters

V IN

http://onsemi.com

SOIC−8 NB

CASE 751

MARKING DIAGRAM

8

PIN CONNECTIONS

COMP

FB

EN

AGND

PG

V IN

V SW

PGND

(Top View)

Device Package Shipping†

ORDERING INFORMATION

NCP3170ADR2G SOIC−8

(Pb−Free)

2500 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our T ape and Reel Packaging Specifications Brochure, BRD8011/D.

NCP3170BDR2G SOIC−8

(Pb−Free)

2500 / Tape & Reel 3170x= Specific Device Code

x = A or B

A= Assembly Location

L= Wafer Lot

Y= Year

W= Work Week

G= Pb−Free PackageFigure 2. NCP3170 Block Diagram VIN

PGND

AGND

PIN FUNCTION DESCRIPTION

Pin Pin Name Description

1PGND The power ground pin is the high current path for the device. The pin should be soldered to a large copper area to reduce thermal resistance. PGND needs to be electrically connected to AGND.

2VIN The input voltage pin powers the internal control circuitry and is monitored by multiple voltage comparators.

The VIN pin is also connected to the internal power PMOS switch and linear regulator output. The VIN pin

has high di/dt edges and must be decoupled to ground close to the pin of the device.

3AGND The analog ground pin serves as small−signal ground. All small−signal ground paths should connect to the AGND pin and should also be electrically connected to power ground at a single point, avoiding any high

current ground returns.

4FB Inverting input to the OTA error amplifier. The FB pin in conjunction with the external compensation serves to stabilize and achieve the desired output voltage with current mode compensation.

5COMP The loop compensation pin is used to compensate the transconductance amplifier which stabilizes the opera-tion of the converter stage. Place compensation components as close to the converter as possible. Connect

a RC network between COMP and AGND to compensate the control loop.

6EN Enable pin. Pull EN to logic high to enable the device. Pull EN to logic low to disable the device. Do not leave it open.

7PG Power good is an open drain 500 m A pull down indicating output voltage is within the power good window. If the power good function is not used, it can be connected to the VSW node to reduce thermal resistance. Do

not connect PG to the VSW node if the application is turning on into pre−bias.

8VSW The VSW pin is the connection of the drains of the internal N and P MOSFETS. At switch off, the inductor will drive this pin below ground as the body diode and the NMOS conducts with a high dv/dt.ABSOLUTE MAXIMUM RATINGS (measured vs. GND pin 3, unless otherwise noted)

Rating Symbol V MAX V MIN Unit Main Supply Voltage Input V IN20−0.3V Voltage between PGND and AGND V PAG0.3−0.3V PWM Feedback Voltage F B6−0.3V Error Amplifier Voltage COMP6−0.3V Enable Voltage EN V IN + 0.3 V−0.3V PG Voltage PG V IN + 0.3 V−0.3V VSW to AGND or PGND V SW V IN + 0.3 V−0.7V VSW to AGND or PGND for 35ns V SWST V IN + 10 V−5V Junction Temperature (Note 1)T J+150°C Operating Ambient Temperature Range T A−40 to +85°C Storage Temperature Range T stg− 55 to +150°C Thermal Characteristics (Note 2)

SOIC−8 Plastic Package

Maximum Power Dissipation @ T A = 25°C Thermal Resistance Junction−to−Air Thermal Resistance Junction−to−Case

P D

R q JA

R q JC

1.15

87

37.8

W

°C/W

°C/W

Lead Temperature Soldering (10 sec):

Reflow (SMD styles only) Pb−Free (Note 3)

RF260 peak°C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

1.The maximum package power dissipation limit must not be exceeded.

P D+T J(max)*T A

R q JA

2.The value of q JA is measured with the device mounted on 2in x 2in FR−4 board with 2oz. copper, in a still air environment with T A = 25°C.

The value in any given application depends on the user’s specific board design.

3.60−180 seconds minimum above 237°C.

RECOMMENDED OPERATING CONDITIONS

Rating Symbol Min Max Unit Main Supply Voltage Input 4.518V

PG 4.518V

V SW−0.318V

EN018V

COMP−0.1 5.5V

FB−0.1 5.5V

PGND−0.1−0.1V Junction Temperature Range T J−40125°C Operating Temperature Range T A−4085°CELECTRICAL CHARACTERISTICS (T A = 25°C, V IN = V EN = 12 V, V OUT = 3.3 V for min/max values unless otherwise noted (Note 7))

Characteristic Conditions Min Typ Max Unit Input Voltage Range(Note 5) 4.518V SUPPLY CURRENT

Quiescent Supply Current NCP3170A

NCP3170B V IN = EN = 12 V V FB= 0.8 V

(Note 5)

1.7

2.0

2.0

2.4

mA

Shutdown Supply Current EN = 0 V (Note 5)1317m A UNDER VOLTAGE LOCKOUT

VIN UVLO Threshold V IN Rising Edge (Note 5) 4.41V VIN UVLO Threshold V IN Falling Edge (Note 5) 4.13V MODULATOR

Oscillator Frequency NCP3170A

NCP3170B Enable = V IN450

900

500

1000

550

1100

kHz

Maximum Duty Ratio9196%

Minimum Duty Ratio NCP3170A

NCP3170B V IN = 12 V 6.0

7.5

%

VIN Soft Start Ramp Time V FB = VCOMP 3.5 4.6 6.0ms OVER CURRENT

Current Limit(Note 4) 4.0 6.0A PWM COMPENSATION

VFB Feedback Voltage T A = 25°C0.7880.80.812V Line Regulation(Note 4)1% GM201m S AOL DC gain(Note 4)4055dB Unity Gain BW (C OUT = 10 pF)(Note 4) 2.0MHz Input Bias Current (Current Out of FB IB Pin)286nA IEAOP Output Source Current V FB = 0 V20.1m A IEAOM Output Sink Current V FB = 2 V21.3m A ENABLE

Enable Threshold(Note 5) 1.41V POWER GOOD

Power Good High On Threshold875mV Power Good High Off Threshold859mV Power Good Low On Threshold712mV Power Good Low Off Threshold728mV Over Voltage Protection Threshold998mV Power Good Low Voltage V IN = 12 V, IPG = 500 m A0.195V PWM OUTPUT STAGE

High−Side Switch On−Resistance V IN = 12 V

V IN = 4.5 V 90

100

130

150

m W

Low−Side Switch On−Resistance V IN = 12 V

V IN = 4.5 V 25

29

35

39

m W

THERMAL SHUTDOWN

Thermal Shutdown(Notes 4 and 6)1°C Hysteresis43°C

4.Guaranteed by design

5.Ambient temperature range of −40°C to +85°C.

6.This is not a protection feature.

7.The device is not guaranteed to operate beyond the maximum operating ratings.

Figure 3. Light Load (DCM) Operation 1 m s/DIV Figure 4. Full Load (CCM) Operation 1 m s/DIV

Figure 5. Start−Up into Full Load 1 ms/DIV Figure 6. Short−Circuit Protection 200 m s /DIV

Figure 7. 50% to 100% Load Transient 100 m s/DIV Figure 8. 3.3 V Turn on into 1 V Pre−Bias 1 ms /DIV

Figure 9. ICC Shut Down Current vs.

Temperature

Figure 10. NCP3170 Enabled Current vs.

Temperature

TEMPERATURE (°C)TEMPERATURE (°C)

Figure 11. Bandgap Reference Voltage vs.

Temperature

Figure 12. Switching Frequency vs.

Temperature

TEMPERATURE (°C)TEMPERATURE (°C)

Figure 13. Input Under Voltage Protection at

12 V vs. Temperature Figure 14. Input Over Voltage Protection at

12 V vs. Temperature

TEMPERATURE (°C)TEMPERATURE (°C)

C U R R E N T

D R A W (m A )

C U R R E N T

D R A W (m A )

B A N D G A P R E F E R E N

C E (m V )

S W I T C H I N G F R E Q U E N C Y (k H z )

T R I P V O L T A G E A T F B P I N (m V )

T R I P V O L T A G E A T F B P I N (m V )

TYPICAL PERFORMANCE CHARACTERISTICS

(Circuit from Figure 1, TA = 25°C, V IN = V EN = 12 V, V OUT = 3.3 V unless otherwise specified)

Figure 15. High Side MOSFET R DS(on) vs.

Temperature Figure 16. Low Side MOSFET R DS(on) vs.

Temperature

TEMPERATURE (°C)TEMPERATURE (°C)

Figure 17. Transconductance vs. Temperature Figure 18. Over Voltage Protection vs.

Temperature

TEMPERATURE (°C)TEMPERATURE (°C)

H

I

G

H

S

I

D

E

M

O

S

F

E

T

R

D

S

(

o

n

)

(

m

W

)

L

O

W

S

I

D

E

M

O

S

F

E

T

R

D

S

(

o

n

)

(

m

W

)

T

R

A

N

S

C

O

N

D

U

C

T

A

N

C

E

(

m

S

)

T

R

I

P

V

O

L

T

A

G

E

A

T

F

B

P

I

N

(

m

V

)

Figure 19. Input Under Voltage Protection vs.

Temperature

T

R

I

P

V

O

L

T

A

G

E

A

T

F

B

P

I

N

(

m

V

)

TEMPERATURE (°C)

Figure 20. Efficiency (V IN = 12 V) vs. Load

Current

Figure 21. Efficiency (V IN = 5 V) vs. Load Current

1

2

3

OUTPUT CURRENT (A)E F F I C I E N C Y (%)

0102030405060708090OUTPUT CURRENT (A)

E F F I C I E N C Y (%)

Thermal derating curves for the SOIC −8 package part under typical input and output conditions based on the evaluation board.The ambient temperature is 25°C with natural convection (air speed < 50LFM) unless otherwise specified.

Figure 22. 500 kHz Derating Curves at 5 V 012345T A , AMBIENT TEMPERATURE (°C)

I O U T , A M B I E N T T E M P E R A T U R E

(°C )

012345Figure 23. 500 kHz Derating Curves at 12 V

T A , AMBIENT TEMPERATURE (°C)

I O U T , A M B I E N T T E M P E R A T U R E (°C )

Figure 24. 12 V, 1 MHz Efficiency

Figure 25. 5 V, 1 MHz Efficiency

OUTPUT CURRENT (A)

E F F I C I E N C Y (%)

OUTPUT CURRENT (A)

E F F I C I E N C Y (%)

Thermal derating curves for the SOIC −8 package part under typical input and output conditions based on the evaluation board.The ambient temperature is 25°C with natural convection (air speed < 50 LFM) unless otherwise specified.

Figure 26. 1 MHz Derating Curves at 5 V Input Figure 27. 1 MHz Derating Curves at 12 V Input

012

345I O U T , A M B I E N T T E M P E R A T U R E (°C )

T A , AMBIENT TEMPERATURE (°C)T A , AMBIENT TEMPERATURE (°C)

012345I O U T , A M B I E N T T E M P E R A T U R E (°C )

DETAILED DESCRIPTION

The NCP3170 is a current −mode, step down regulator with an integrated high −side PMOS switch and a low −side NMOS switch. It operates from a 4.5 V to 18 V input voltage range and supplies up to 3 A of load current. The duty ratio can be adjusted from 8% to 92% allowing a wide output voltage range. Features include enable control, Power −On Reset (POR), input under voltage lockout, fixed internal soft start, power good indication, over voltage protection, and thermal shutdown.

Enable and Soft −Start

An internal input voltage comparator not shown in Figure 28 will force the part to disable below the minimum input voltage of 4.13 V . The input under voltage disable feature is used to prevent improper operation of the converter due to insufficient voltages. The converter can be turned on by tying the enable pin high and the part will default to be input voltage enabled. The enable pin should never be left floating.

Figure 28. Input Voltage Enable

If an adjustable Under V oltage Lockout (UVLO)threshold is required, the EN pin can be used. The trip voltage of the EN pin comparator is 1.38 V typical. Upon application of an input voltage greater than 4.41 V , the VIN UVLO will release and the enable will be checked to determine if switching can commence. Once the 1.38 V trip voltage is crossed, the part will enable and the soft start sequence will initiate. If large resistor values are used, the EN pin should be bypassed with a 1 nF capacitor to prevent coupling problems from the switch node.

Figure 29. Input Under Voltage Lockout Enable

C1The enable pin can be used to delay a turn on by

connecting a capacitor as shown in Figure 30.

Figure 30. Delay Enable

If the designer would like to add hysteresis to the enable threshold it can be added by use of a bias resistor to the output. The hysteresis is created once soft start has initiated.With the output voltage rising, current flows into the enable node, raising the voltage. The thresholds for enable as well as hysteresis can be calculated using Equation 1.

VIN HYS +VIN Start *EN TH )R1UV

(eq. 1)

ƪ

V OUT *EN TH

R3UV

*

EN TH R2UV

ƫ

VIN Start +EN TH ƪ

1)

R1UV ǒR2UV )R3UV Ǔ

R2UV R3UV

ƫ

EN TH

= Enable Threshold

VIN START = Input V oltage Start Threshold R1UV = High Side Resistor R2UV = Low Side Resistor

R3UV = Hysteresis Bias Resistor VOUT = Regulated Output V oltage

Figure 31. Added Hysteresis to the Enable UVLO

Figure 32. Logic Turn−on

The enable can also be used for power sequencing in conjunction with the Power Good (PG) pin as shown in Figure 33. The enable pin can either be tied to the output voltage of the master voltage or tied to the input voltage with a resistor to the PG pin of the master regulator.

Figure 33. Enable Two Converter Power Sequencing

Once the part is enabled, the internal reference voltage is slewed from ground to the set point of 800 mV. The slewing process occurs over a 4.5 ms period, reducing the current draw from the upstream power source, reducing stress on internal MOSFETS, and ensuring the output inductor does not saturate during start−up.

Pre−Bias Start−up

When starting into a pre−bias load, the NCP3170 will not discharge the output capacitors. The soft start begins with the internal reference at ground. Both the high side switch and low side switches are turned off. The internal reference slowly raises and the OTA regulates the output voltage to the divided reference voltage. In a pre−biased condition, the voltage at the FB pin is higher than the internal reference voltage, so the OTA will keep the COMP voltage at ground potential. As the internal reference is slewed up, the COMP pin is held low until the FB pin voltage surpasses the internal reference voltage, at which time the COMP pin is allowed to respond to the OTA error signal. Since the bottom of the PWM ramp is at 0.6 V there will be a slight delay between the time the internal reference voltage passes the FB voltage and when the part starts to switch. Once the COMP error signal intersects with the bottom of the ramp, the high side switch is turned on followed by the low side switch. After the internal reference voltage has surpassed the FB voltage, soft start proceeds normally without output voltage discharge. Power Good

The output voltage of the buck converter is monitored at the feedback pin of the output power stage. Two comparators are placed on the feedback node of the OTA to monitor the operating window of the feedback voltage as shown in Figure 34. All comparator outputs are ignored during the soft start sequence as soft start is regulated by the OTA since false trips would be generated. Further, the PG pin is held low until the comparators are evaluated. PG state does not affect the switching of the converter. After the soft start period has ended, if the feedback is below the reference voltage of comparator 1 (V FB < 0.726), the output is considered operational undervoltage (OUV). The device will indicate the under voltage situation by the PG pin remaining low with a 100 k W pull−up resistance. When the feedback pin voltage rises between the reference voltages of comparator 1 and comparator 2 (0.726 < V FB < 0.862), then the output voltage is considered power good and the PG pin is released. Finally, if the feedback voltage is greater than comparator 2 (V FB > 0.862), the output voltage is considered operational overvoltage (OOV). The OOV will be indicated by the PG pin remaining low. A block diagram of the OOV and OUV functionality as well as a graphical representation of the PG pin functionality is shown in Figures 34 through 36.

Figure 34. OOV and OUV System

Figure 35. OOV and OUV Window

Figure 36. OOV and OUV Diagram

If the power good function is not used, it can be connected to the VSW node to reduce thermal resistance. Do not connect PG to the VSW node if the application is turning on into pre−bias.

Switching Frequency

The NCP3170 switching frequency is fixed and set by an internal oscillator. The practical switching frequency could range from 450 kHz to 550 kHz for the NCP3170A and 900 kHz to 1.1 MHz for the NCP3170B due to device variation.

Light Load Operation

Light load operation is generally a load that is 1mA to 300 mA where a load is in standby mode and requires very little power. During light load operation, the regulator emulates the operation of a non−synchronous buck converter and the regulator is allowed to skip pulses. The non−synchronous buck emulation is accomplished by detecting the point at which the current flowing in the inductor goes to zero and turning the low side switch off. At the point when the current goes to zero, if the low side switch is not turned off, current would reverse, discharging the output capacitor. Since the low side switch is shutoff, the only conduction path is through the body diode of the low side MOSFET, which is back biased. Unlike traditional synchronous buck converters, the current in the inductor will become discontinuous. As a result, the switch node will oscillate with the parasitic inductances and capacitances connected to the switch node. The OTA will continue to regulate the output voltage, but will skip pulses based on the

output load shown in Figure 37.

Figure 37. Light Load Operation Protection Features

Over Current Protection

Current is limited to the load on a pulse by pulse basis. During each high side on period, the current is compared against an internally set limit. If the current limit is exceeded, the high side and low side MOSFETS are shutoff and no pulses are issued for 13.5 m s. During that time, the output voltage will decay and the inductor current will discharge. After the discharge period, the converter will initiate a soft start. If the load is not released, the current will build in the inductor until the current limit is exceeded, at which time the high side and low side MOSFETS will be shut off and the process will continue. If the load has been released, a normal soft start will commence and the part will continue switching normally until the current limit is

exceeded.

Figure 38. Over Current Protection Thermal Shutdown

The thermal limit, while not a protection feature, engages at 150°C in case of thermal runaway. When the thermal comparator is tripped at a die temperature of 150°C, the part must cool to 120°C before a restart is allowed. When thermal trip is engaged, switching ceases and high side and low side MOSFETs are driven off. Further, the power good indicator will pull low until the thermal trip has been released. Once the die temperature reaches 120°C the part will reinitiate soft−start and begin normal operation.

Figure 39. Over Temperature Shutdown

Over Voltage Protection

Upon the completion of soft start, the output voltage of the buck converter is monitored at the FB pin of the output power stage. One comparator is placed on the feedback node to provide over voltage protection. In the event an over voltage is detected, the high side switch turns off and the low side switch turns on until the feedback voltage falls below the OOV threshold. Once the voltage has fallen below the OOV threshold, switching continues normally as displayed in Figure 40.

Figure 40. Over Voltage Low Side Switch Behavior Duty Ratio

The duty ratio can be adjusted from 8% to 92% allowing a wide output voltage range. The low 8% duty ratio limit will restrict the PWM operation. For example if the application is converting to 1.2V the converter will perform normally if the input voltage is below 15.5V. If the input voltage exceeds 15.5V while supplying 1.2V output voltage the converter can skip pulses during operation. The skipping pulse operation will result in higher ripple voltage than when operating in PWM mode. Figure 41 and 42 below shows the safe operating area for the NCP3170A and B respectively. While not shown in the safe operating area graph, the output voltage is capable of increasing to the 93% duty ratio limitation providing a high output voltage such as 16V. If the application requires a high duty ratio such as converting from 14V to 10V the converter will operate normally until the maximum duty ratio is reached. For example, if the input voltage were 16V and the user wanted to produce the highest possible output voltage at full load, a good rule of thumb is to use 80% duty ratio. The discrepancy between the usable duty ratio and the actual duty ratio is due to the voltage drops in the system, thus leading to a maximum output voltage of 12.8V rather than 14.8V. The actual achievable output to input voltage ratio is dependent on layout, component selection, and acceptable output voltage tolerance.

Figure 41. NCP3170A Safe Operating Area

Figure 42. NCP3170B Safe Operating Area Design Procedure

When starting the design of a buck regulator, it is important to collect as much information as possible about the behavior of the input and output before starting the design.

ON Semiconductor has a Microsoft Excel® based design tool available online under the design tools section of the NCP3170 product page. The tool allows you to capture your design point and optimize the performance of your regulator based on your design criteria.

DESIGN PARAMETERS

Design Parameter Example Value Input Voltage (V IN)9 V to 16 V Output Voltage (V OUT) 3.3 V

Input Ripple Voltage (VCC RIPPLE)200 mV Output Ripple Voltage (V OUTRIPPLE)20 mV

Output Current Rating (I OUT) 3 A Operating Frequency (F SW)500 kHzThe buck converter produces input voltage (V IN) pulses that are LC filtered to produce a lower DC output voltage (V OUT). The output voltage can be changed by modifying the on time relative to the switching period (T) or switching frequency. The ratio of high side switch on time to the switching period is called duty ratio (D). Duty ratio can also be calculated using V OUT, V IN, the Low Side Switch V oltage Drop (V LSD), and the High Side Switch V oltage Drop (V HSD).

F SW+1

T

(eq. 2)

D+T ON

T

(1*D)+

T OFF

T

(eq. 3)

D+

V OUT)V LSD

V IN*V HSD)V LSD

[

(eq. 4)

D+V OUT

V IN

³27.5%+

3.3V

12V

D= Duty ratio

FSW= Switching frequency

T= Switching period

TOFF= High side switch off time

TON= High side switch on time

V IN= Input voltage

VHSD= High side switch voltage drop

VLSD= Low side switch voltage drop

VOUT= Output voltage

Inductor Selection

When selecting an inductor, the designer may employ a rule of thumb for the design where the percentage of ripple current in the inductor should be between 10% and 40%. When using ceramic output capacitors, the ripple current can be greater because the ESR of the output capacitor is smaller, thus a user might select a higher ripple current. However, when using electrolytic capacitors, a lower ripple current will result in lower output ripple due to the higher ESR of electrolytic capacitors. The ratio of ripple current to maximum output current is given in Equation 5.

ra+

D I

I OUT(eq. 5)

D I = Ripple current

I OUT= Output current

ra = Ripple current ratio

Using the ripple current rule of thumb, the user can establish acceptable values of inductance for a design using Equation 6.

L OUT+

V OUT

I OUT ra F SW

(1*D)³

(eq. 6)

4.7m H+

12V

3.0A34%500kHz

(1*27.5%)

D= Duty ratio

F SW= Switching frequency

I OUT= Output current

L OUT= Output inductance

ra = Ripple current ratio

4.7 m H

7 V

4.4 V

Figure 43. Inductance vs. Current Ripple Ratio

18 V

19

17

15

13

11

9

7

5

3

1

1013161922252831343740

RIPPLE CURRENT RATIO (%)

I

N

D

U

C

T

A

N

C

E

(

m

H

)

When selecting an inductor, the designer must not exceed

the current rating of the part. To keep within the bounds of

the part’s maximum rating, a calculation of the RMS current

and peak current are required.

I RMS+I OUT1)

ra2

12

Ǹ³

(eq. 7)

3.01A+3A1)

34%2

12

Ǹ³

I OUT= Output current

I RMS= Inductor RMS current

ra = Ripple current ratio

I PK+I OUTǒ1)ra2Ǔ³

(eq. 8)

3.51A+3Aǒ1)34%2

I OUT= Output current

I PK= Inductor peak current

ra = Ripple current ratio

A standard inductor should be found so the inductor will be rounded to 4.7 m H. The inductor should support an RMS current of 3.01 A and a peak current of 3.51 A. A good design practice is to select an inductor that has a saturation current that exceeds the maximum current limit with some margin.The final selection of an output inductor has both mechanical and electrical considerations. From a mechanical perspective, smaller inductor values generally correspond to smaller physical size. Since the inductor is often one of the largest components in the regulation system,a minimum inductor value is particularly important in space constrained applications. From an electrical perspective, the maximum current slew rate through the output inductor for a buck regulator is given by Equation 9.

SlewRate LOUT +

V IN *V OUT

L OUT

³

(eq. 9)

1.85

A m s +12V *3.3V 4.7m H

L OUT = Output inductance

V IN = Input voltage V OUT = Output voltage

Equation 9 implies that larger inductor values limit the regulator’s ability to slew current through the output inductor in response to output load transients. Consequently,output capacitors must supply the load current until the inductor current reaches the output load current level.Reduced inductance to increase slew rates results in larger values of output capacitance to maintain tight output voltage regulation. In contrast, smaller values of inductance increase the regulator’s maximum achievable slew rate and decrease the necessary capacitance at the expense of higher ripple current. The peak −to −peak ripple current for NCP3170 is given by the following equation:

I PP +V OUT (1*D )L OUT F SW

³

(eq. 10)

1.02A +

3.3V (1*27.5%)

4.7m H 500kHz

D = Duty ratio F SW = Switching frequency I PP =

Peak −to −peak current of the inductor L OUT = Output inductance V OUT

=

Output voltage

From Equation 10, it is clear that the ripple current increases as L OUT decreases, emphasizing the trade −off between dynamic response and ripple current.

The power dissipation of an inductor falls into two categories: copper and core losses. Copper losses can be further categorized into DC losses and AC losses. A good first order approximation of the inductor losses can be made using the DC resistance as shown below:

LP CU_DC +I RMS 2 DCR ³(eq. 11)

61mW +3.012 6.73m W

DCR = Inductor DC resistance I RMS = Inductor RMS current

LP CU_DC = Inductor DC power dissipation

The core losses and AC copper losses will depend on the geometry of the selected core, core material, and wire used.Most vendors will provide the appropriate information to make accurate calculations of the power dissipation at which point the total inductor losses can be captured by the equation below:

LP tot +LP CU_DC )LP CU_AC )LP Core ³(eq. 12)

67mW +61mW )5mW )1mW

LP Core = Inductor core power dissipation LP CU_AC = Inductor AC power dissipation LP CU_DC = Inductor DC power dissipation LP tot

= Total inductor losses

Output Capacitor Selection

The important factors to consider when selecting an output capacitor are DC voltage rating, ripple current rating,output ripple voltage requirements, and transient response requirements.

The output capacitor must be able to operate properly for the life time of a product. When selecting a capacitor it is important to select a voltage rating that is de −rated to the guaranteed operating life time of a product. Further, it is important to note that when using ceramic capacitors, the capacitance decreases as the voltage applied increases; thus a ceramic capacitor rated at 100 m F 6.3 V may measure 100 m F at 0 V but measure 20 m F with an applied voltage of 3.3 V depending on the type of capacitor selected.

The output capacitor must be rated to handle the ripple current at full load with proper derating. The capacitor RMS ratings given in datasheets are generally for lower switching frequencies than used in switch mode power supplies, but a multiplier is given for higher frequency operation. The RMS current for the output capacitor can be calculated below:

CO RMS +I OUT

ra

12

Ǹ³(eq. 13)

0.294A +3.0A

34%

12

ǸCo RMS = Output capacitor RMS current I OUT = Output current ra = Ripple current ratio

The maximum allowable output voltage ripple is a combination of the ripple current selected, the output capacitance selected, the Equivalent Series Inductance (ESL), and Equivalent Series Resistance (ESR).

The main component of the ripple voltage is usually due to the ESR of the output capacitor and the capacitance selected, which can be calculated as shown in Equation 14:

V ESR_C +I OUT ra ǒ

CO ESR )

1

8 F SW C OUT

Ǔ

³

(eq. 14)

10.mV +3 34% ǒ

5m W )

1

8 500kHz 44m F

Ǔ

Co ESR = Output capacitor ESR C OUT = Output capacitance F SW = Switching frequency I OUT = Output current ra = Ripple current ratio

V ESR_C = Ripple voltage from the capacitor

The impedance of a capacitor is a function of the frequency of operation. When using ceramic capacitors, the ESR of the capacitor decreases until the resonant frequency is reached, at which point the ESR increases; therefore the ripple voltage might not be what one expected due to the switching frequency. Further, the method of layout can add resistance in series with the capacitance, increasing ripple voltage.

The ESL of capacitors depends on the technology chosen,but tends to range from 1 nH to 20 nH, where ceramic capacitors have the lowest inductance and electrolytic capacitors have the highest. The calculated contributing voltage ripple from ESL is shown for the switch on and switch off below:

V ESLON +

ESL I PP F SW

D

³

(eq. 15)

1.84mV +

1nH @1.01A @500kHz

27.5%

V ESLOFF +

ESL I PP F SW

(1*D )

³

(eq. 16)

0.7mV +

1nH 1.1A 500kHz

(1*27.5%)

D = Duty ratio

ESL = Capacitor inductance F SW = Switching frequency I PP

= Peak −to −peak current

The output capacitor is a basic component for fast response of the power supply. For the first few microseconds of a load transient, the output capacitor supplies current to the load. Once the regulator recognizes a load transient, it adjusts the duty ratio, but the current slope is limited by the inductor value.

During a load step transient, the output voltage initially drops due to the current variation inside the capacitor and the ESR (neglecting the effect of the ESL).

D V OUT −ESR +I TRAN CO ESR ³

(eq. 17)

7.5mV +1.5A 5m W

Co ESR =Output capacitor Equivalent Series

Resistance

I TRAN = Output transient current

D V OUT _ESR =V oltage deviation of V OUT due to the

effects of ESR A minimum capacitor value is required to sustain the current during the load transient without discharging it. The voltage drop due to output capacitor discharge is given by the following equation:

D V OUT −DIS +

ǒI TRAN Ǔ

2

L OUT F SW

2 F CROSS C OUT ǒV IN *V OUT Ǔ³(eq. 18)

133.5mV +

(1.5)2

4.7m H 500kHz

2 50kHz 44m F ǒ12V *3.3V Ǔ

C OUT = Output capacitance

D = Duty ratio F SW = Switching frequency

F CROSS = Loop cross over frequency I TRAN = Output transient current L OUT = Output inductor value V IN = Input voltage V OUT = Output voltage

D V OUT _DIS = V oltage deviation of V OUT due to the

effects of capacitor discharge In a typical converter design, the ESR of the output capacitor bank dominates the transient response. Please note that D V OUT _DIS and D V OUT_ESR are out of phase with each other, and the larger of these two voltages will determine the maximum deviation of the output voltage (neglecting the effect of the ESL). It is important to note that the converters frequency response will change when the NCP3170 is operating in synchronous mode or non −synchronous mode due to the change in plant response from CCM to DCM. The effect will be a larger transient voltage excursion when transitioning from no load to full load quickly.

Input Capacitor Selection

The input capacitor has to sustain the ripple current produced during the on time of the upper MOSFET, so it must have a low ESR to minimize losses and input voltage ripple. The RMS value of the input ripple current is:

Iin RMS

+I OUT

D (1*D )Ǹ³

(eq. 19)

1.34A +3A 27.5% (1*27.5%)

ǸD = Duty ratio

Iin RMS = Input capacitance RMS current I OUT =

Load current

The equation reaches its maximum value with D = 0.5 at which point the input capacitance RMS current is half the

output current. Loss in the input capacitors can be calculated

with the following equation:

P CIN +CIN ESR ǒIin RMS Ǔ

2(eq. 20)

18mW +10m W ǒ1.34A Ǔ

2

CIN ESR =Input capacitance Equivalent Series Resistance

Iin RMS = Input capacitance RMS current P CIN

= Power loss in the input capacitor

Due to large di/dt through the input capacitors, electrolytic or ceramics should be used. If a tantalum capacitor must be used, it must be surge protected, otherwise capacitor failure could occur.

Power MOSFET Dissipation

Power dissipation, package size, and the thermal environment drive power supply design. Once the dissipation is known, the thermal impedance can be calculated to prevent the specified maximum junction temperatures from being exceeded at the highest ambient temperature.

Power dissipation has two primary contributors:conduction losses and switching losses. The high −side MOSFET will display both switching and conduction losses. The switching losses of the low side MOSFET will not be calculated as it switches into nearly zero voltage and the losses are insignificant. However, the body diode in the low −side MOSFET will suffer diode losses during the non −overlap time of the gate drivers.

Starting with the high −side MOSFET, the power dissipation can be approximated from:

P D_HS +P COND )P SW_TOT

(eq. 21)

P COND = Conduction losses

P D_HS = Power losses in the high side MOSFET P SW_TOT

= Total switching losses

The first term in Equation 21 is the conduction loss of the high −side MOSFET while it is on.

P COND +ǒI RMS_HS

Ǔ

2

R DS(on)_HS

(eq. 22)

I RMS_HS = RMS current in the high side MOSFET R DS(ON)_HS = On resistance of the high side MOSFET P COND = Conduction power losses Using the ra term from Equation 5, I RMS becomes:

I RMS_HS +I OUT

D ǒ

1)

ra 2

12

Ǔ

Ǹ(eq. 23)

D =

Duty ratio ra = Ripple current ratio I OUT = Output current I RMS_HS = High side MOSFET RMS current The second term from Equation 21 is the total switching loss and can be approximated from the following equations.

P SW_TOT +P SW )P DS )P RR

(eq. 24)

P DS

= High side MOSFET drain to source losses P RR = High side MOSFET reverse recovery losses

P SW

= High side MOSFET switching losses

P SW_TOT

= High side MOSFET total switching losses

The first term for total switching losses from Equation 24are the losses associated with turning the high −side MOSFET on and off and the corresponding overlap in drain voltage and current.

P SW +P TON )P TOFF +

1

2 ǒI OUT V IN F SW Ǔ(eq. 25)

ǒt RISE )t FALL Ǔ

F SW = Switching frequency

I OUT = Load current P SW = High side MOSFET switching losses P TON = Turn on power losses P TOFF = Turn off power losses t FALL = MOSFET fall time t RISE = MOSFET rise time V IN = Input voltage When calculating the rise time and fall time of the high

side MOSFET, it is important to know the charge characteristic shown in Figure 44.

Figure 44. High Side MOSFET Total Charge

Vth

t RISE +

Q GD I G1

+

Q GD

ǒV CL *V TH ǓńǒR HSPU )R G Ǔ

(eq. 26)

IG1= Output current from the high −side gate drive Q GD = MOSFET gate to drain gate charge R HSPU = Drive pull up resistance R G = MOSFET gate resistance t RISE = MOSFET rise time V CL = Clamp voltage

V TH

= MOSFET gate threshold voltage

I G2

+

Q GD

ǒV

CL

*V THǓńǒR HSPD)R GǓ

(eq. 27)

IG2 = Output current from the low−side gate

drive

Q GD= MOSFET gate to drain gate charge

R G= MOSFET gate resistance

R HSPD= Drive pull down resistance

t FALL= MOSFET fall time

V CL= Clamp voltage

V TH= MOSFET gate threshold voltage Next, the MOSFET output capacitance losses are caused by both the high−side and low−side MOSFETs, but are dissipated only in the high−side MOSFET.

P DS+1

2

@C OSS@V IN2@F SW(eq. 28)

C OSS= MOSFET output capacitance at 0 V

F SW= Switching frequency

P DS= MOSFET drain to source charge losses

V IN= Input voltage

Finally, the loss due to the reverse recovery time of the body diode in the low−side MOSFET is shown as follows:

P RR+Q RR V IN F SW(eq. 29) F SW= Switching frequency

P RR= High side MOSFET reverse recovery

losses

Q RR= Reverse recovery charge

V IN= Input voltage

The low−side MOSFET turns on into small negative voltages so switching losses are negligible. The low−side MOSFET’s power dissipation only consists of conduction loss due to R DS(on)and body diode loss during non−overlap periods.

P D_LS+P COND)P BODY(eq. 30) P BODY= Low side MOSFET body diode losses

P COND= Low side MOSFET conduction losses

P D_LS= Low side MOSFET losses Conduction loss in the low−side MOSFET is described as follows:

P COND+ǒI RMS_LSǓ2R DS(on)_LS(eq. 31) I RMS_LS = RMS current in the low side

R DS(ON)_LS = Low−side MOSFET on resistance

P COND= High side MOSFET conduction losses

I RMS_LS+I OUT(1*D)ǒ1)ra212Ǔ

Ǹ(eq. 32) D

=

Duty

ratio

I OUT

=

Load

current

I RMS_LS= RMS current in the low side

ra = Ripple current ratio

The body diode losses can be approximated as:

P BODY+V FD@I OUT@F SW@ǒNOL LH)NOL HLǓ(eq. 33) F SW= Switching frequency

I OUT

=

Load

current

NOL HL = Dead time between the high−side

MOSFET turning off and the low−side

MOSFET turning on, typically 30 ns NOLLH

=

Dead

time between the low−side MOSFET

turning off and the high−side MOSFET

turning on, typically 30 ns

P BODY= Low−side MOSFET body diode losses

V FD = Body diode forward voltage drop typically

0.92 V

Compensation Network

To create a stable power supply, the compensation network around the transconductance amplifier must be used in conjunction with the PWM generator and the power stage. Since the power stage design criteria is set by the application, the compensation network must correct the overall output to ensure stability. The NCP3170 is a current mode regulator and as such there exists a voltage loop and a current loop. The current loop causes the inductor to act like a current source which governs most of the characteristics of current mode control. The output inductor and capacitor of the power stage form a double pole but because the inductor is treated like a current source in closed loop, it becomes a single pole system. Since the feedback loop is controlling the inductor current, it is effectively like having a current source feeding a capacitor; therefore the pole is controlled by the load and the output capacitance. A table of compensation values for 500 kHz and 1 MHz is provided below for two 22 m F ceramic capacitors. The table also provides the resistor value for CompCalc at the defined operating point.

VIN (V)V out

(V)

L out

(m F)

R1

(k W)

R2

(k W)

Rf

(k W)

Cf

(pF)

Cc

(nF)

Rc

(k W)

Cp

(pF)

Resistance for

Current Gain

NCP3170A 120.8 1.824.9NI NI NI NI NI15 3.6 12 1.0 2.524.91001150150.825NI4 12 1.1 2.524.966.51150102NI20 12 1.2 2.524.949.91150102NI20 12 1.5 3.624.928.7115010 2.49NI20 12 1.8 3.624.920115010 2.49NI20 12 2.5 4.724.911.811508.2 3.74NI25 12 3.3 4.724.97.871150 6.8 4.99NI27 12 5.07.224.9 4.751150 3.910NI27 1210.687.224.9 2.051150 3.910NI30 1814.87.224.9 1.431150 6.8 6.98NI30 50.8 1.824.9NI NI NI NI NI1515 5 1.0 2.524.91001150150.825NI28 5 1.1 2.524.966.51150102NI30 5 1.2 2.524.949.91150102NI30 5 1.5 3.624.928.7115010 2.49NI30 5 1.8 3.624.920115010 2.49NI30 5 2.5 3.624.911.81150 6.8 4.99NI50 5 3.3 3.624.97.871150 6.8 4.99NI50

NCP3170B 12 1.2 1.524.949.9182 2.7 6.04NI20 12 1.5 1.824.928.7182 2.7 6.04NI22 12 1.8 1.824.920182 2.7 6.04NI22 12 2.5 2.724.911.8182 1.810NI32 12 3.3 3.324.97.87182 1.512.1NI52 12 5.0 3.324.9 4.75182 2.28.25NI52 1210.68 1.524.9 2.05182 2.2 5.1NI52 1814.8 3.324.9 1.43182 2.2 5.1NI52 50.8 1.024.9NI NI NI150.499NI20 5 1.0 1.024.9100NI NI 6.8 1.69NI28 5 1.1 1.024.966.5NI NI 3.9 3.61NI42 5 1.2 1.524.949.9182 2.7 6.04NI55 5 1.5 1.524.928.7182 2.7 6.04NI55 5 1.8 1.524.920182 1.810NI55 5 2.5 1.824.911.8182 1.810NI55 5 3.3 1.824.97.87182 1.810NI55

To compensate the converter we must first calculate the current feedback

M +

V IN )1.83V

W

@F SW @L OUT

V IN

(eq. 34)

1.358W +

12V )1.83

V W 500kHz 4.7m H

12V F SW =

Switching Frequency L OUT = Output inductor value M = Current feedback V IN = Input V oltage

Next the DC gain of the plant must be calculated.

G +

V OUT L OUT FSW

0.0088W

ǒL OUT FSW I OUT )V O M *

V

O

2

)

V

O

2 M V

IN

Ǔ

(eq. 35)

25.1+

3.3V

4.7m H 500kHz

0.0088W

ǒ

4.7m H 500kHz 3.0A )3.3V 1.358*

3.3V 2

)

ǒ3.3V Ǔ2 1.359

12V

Ǔ

F SW = Switching Frequency

G = DC gain of the plant L OUT = Output inductor value I OUT =

Output current M = Current feedback V IN = Input voltage V OUT = Output voltage

The un −scaled gain of the converter also needs to be calculated as follows:

A +

1

I OUT VO

)

M *0.5*M

V OUT

V IN

L OUT FSW

(eq. 36)

1.254W +

1

3.0A 3.3V

)

1.358*0.5*1.359

3.3V

12V

4.7m H 500kHz

A = Un −scaled gain F SW = Switching Frequency I OUT =

Output Current L OUT = Output inductor value M = Current feedback V IN = Input V oltage V OUT =

Output V oltage

The amplitude ratio can be calculated using the following equation:

Y +VREF

V OUT ³0.242+

0.8V 3.3V

(eq. 37)

V o = Output voltage VREF = Regulator reference voltage Y = Amplitude ratio

The ESR of the output capacitor creates a “zero” at the frequency as shown in Equation 38:

FZ ESR +

1

2p CO ESR C OUT

³

(eq. 38)

723kHz +

1

2p 0.005m W 44m F

CO ESR

= Output capacitor ESR C OUT = Output capacitor

FZ ESR

= Output capacitor zero ESR frequency

F P +

1

2p A C OUT

³

(eq. 39)

2.885kHz +

1

2p 1.358W 44m F

A =

Un −scaled gain C O UT = Output capacitor F P = Current mode pole frequency

The two equations above define the bode plot that the power stage has created or open loop response of the system.The next step is to close the loop by considering the feedback values. The closed loop crossover frequency should be less than 1/10 of the switching frequency, which would place the maximum crossover frequency at 50 kHz.

Figure 45 shows a pseudo Type III transconductance error amplifier.

Figure 45. Pseudo Type III Transconductance Error

Amplifier

The compensation network consists of the internal error amplifier and the impedance networks Z IN (R 1, R 2, and C F )and external Z FB (R C , C C , and C P ). The compensation network has to provide a closed loop transfer function with the highest 0dB crossing frequency to have fast response and the highest gain in DC conditions, so as to minimize load regulation issues. A stable control loop has a gain crossing with −20 dB/decade slope and a phase margin greater than 45°. Include worst −case component variations when determining phase margin. To start the design, a resistor value should be chosen for R 1 from which all other components can be chosen. A good starting value is 24.9 k W .The NCP3170 allows the output of the DC −DC regulator to be adjusted down to 0.8 V via an external resistor divider network. The regulator will maintain 0.8 V at the feedback pin. Thus, if a resistor divider circuit was placed across the feedback pin to V OUT , the regulator will regulate the output voltage proportional to the resistor divider network in order to maintain 0.8 V at the FB pin.

Figure 46. Feedback Resistor Divider

The relationship between the resistor divider network above and the output voltage is shown in Equation 40:

R 2+R 1

ǒ

V REF

V OUT *V REF

Ǔ

(eq. 40)

R 1= Top resistor divider R 2= Bottom resistor divider V OUT =

Output voltage V REF = Regulator reference voltage

The most frequently used output voltages and their associated standard R 1 and R 2 values are listed in the table below.

OUTPUT VOLTAGE SETTINGS

V O (V)R 1 (k W )R 2 (k W )0.8

24.9Open 1.024.91001.124.966.51.2

24.949.91.524.928.71.824.9202.524.911.83.324.98.065.0

24.9

4.

The compensation components for the Pseudo Type III Transconductance Error Amplifier can be calculated using the method described below. The method serves to provide a good starting place for compensation of a power supply.The values can be adjusted in real time using the compensation tool CompCalc http://www.onsemi.com/pub/Collateral/COMPCALC.ZIP The first pole to crossover at the desired frequency should be setup at FPO to decrease at −20dB per decade:

F PO +

F CROSS

G ³

(eq. 41)

1.99kHz +

50kHz 42.65

³

F cross = Cross over frequency

F PO = Pole frequency to meet crossover frequency

G = DC gain of the plant

The crossover combined compensation network can be used to calculate the transconductance output compensation network as follows:

C C +

y gm 2 p F PO

*³

(eq. 42)

15.4nF +

0.242 200m s 2p 1.994kHz

C C = Compensation capacitor F PO

= Pole frequency

R C+

1

2p C C F P

³

(eq. 43)

14.25k W+

1

2p 3.87nF 2.885kHz

C C = Compensation capacitance C OUT = Output capacitance

F P = Current mode pole frequency R C= Compensation resistor

C P+

1

R C2p F ESR

³

(eq. 44)

15.4fF+

1

14.25k W2p723MHz

C P = Compensation pole capacitor

F ESR = Capacitor ESR zero frequency

R C= Compensation resistor

If the ESR frequency is greater than the switching frequency, a CF compensation capacitor may be needed for stability as the output LC filter is considered high Q and thus will not give the phase boost at the crossover frequency.

C F+

gm

2p@5@F CROSS

³

(eq. 45)

127pF+

200m s

2p550kHz

C F = Compensation pole capacitor

F cross= Cross over frequency

gm = Transconductance of amplifier Calculating Input Inrush Current

The input inrush current has two distinct stages: input charging and output charging. The input charging of a buck stage is usually controlled, but there are times when it is not and is limited only by the input RC network, and the output impedance of the upstream power stage. If the upstream power stage is a perfect voltage source and switches on instantaneously, then the input inrush current can be depicted as shown in Figure 47 and calculated as:

Figure 47. Input Charge Inrush Current

I ICinrush_PK1+

V IN

CIN ESR(eq. 46)

1.2kA+

12

0.01

I ICinrush_RMS1+

V IN

CIN ESR

0.316

5CIN ESR C IN

t DELAY_TOTAL

Ǹ

(eq. 47)

12.58A+

12V

0.01

0.316

1ms

Ǹ

C IN= Output capacitor

CIN ESR= Output capacitor ESR

t DELAY_TOTAL= Total delay interval

V IN= Input V oltage

Once the t DELAY_TOTAL has expired, the buck converter

starts to switch and a second inrush current can be

calculated:

I OCinrush_RMS+

ǒC

OUT

)C LOADǓV OUT

t SS

D

3Ǹ

)I CL D

(eq. 48)

C OUT= Total converter output capacitance

C LOAD= Total load capacitance

D = Duty ratio of the load

I CL= Applied load at the output

I OCinrush_RMS= RMS inrush current during start−up

t SS= Soft start interval

V OUT= Output voltage

From the above equation, it is clear that the inrush current

is dependent on the type of load that is connected to the

output. Two types of load are considered in Figure 48: a

resistive load and a stepped current load.

If the load is resistive in nature, the output current will

increase with soft start linearly which can be quantified in

Equation 49.

I CLR_RMS+

1

3Ǹ

V OUT

R OUT

(eq. 49)

I CR_PK+

V OUT

R OUT

191mA+

1

3Ǹ

3.3V

10W

300mA+

3.3V

10W

I CLR_RMS= RMS resistor current

I CR_PK= Peak resistor current

R OUT= Output resistance

V OUT= Output voltage

3.3 V

Alternatively, if the output load has an under voltage lockout, turns on at a defined voltage level, and draws a constant current, then the RMS connected load current is:

I CL1+

V OUT *V OUT_TO

V OUT

Ǹ

I OUT

(eq. 50)

492mA +

3.3V *2.5V

3.3V

Ǹ

1A

I OUT = Output current V OUT = Output voltage

V OUT_TO

= Output voltage load turn on

Figure 50. Voltage Enable Load Current

If the inrush current is higher than the steady state input current during max load, then an input fuse should be rated accordingly using I 2t methodology.

Thermal Management and Layout

Consideration

In the NCP3170 buck regulator high pulsing current flows through two loops as shown in the figure below.

F

The first loop shown in blue activates when the high side switch turns on. When the switch turns on, the edge of the current waveform is provided by the bypass capacitor. The remainder of the current is provided by the input capacitor.Slower currents are provided by the upstream power supply which fills up the input capacitor when the high side switch is off. The current flows through the high side MOSFET and to the output, charging the output capacitors and providing current to the load. The current returns through a PCB ground trace where the output capacitors are connected, the regulator is grounded, and the input capacitors are grounded.The second loop starts from the inductor to the output capacitors and load, and returns through the low side MOSFET. Current flows in the second loop when the low side NMOSFET is on. The designer should note that there are locations where the red line and the blue line overlap;these areas are considered to have DC current. Areas containing a single blue line indicate that AC currents flow and transition very quickly. The key to power supply layout is to focus on the connections where the AC current flows.A good rule of thumb is that for every inch of PCB trace,20nH of inductance exists. When laying out a PCB,minimizing the AC loop area reduces the noise of the circuit and improves efficiency. A ground plane is strongly recommended to connect the input capacitor, output capacitor, and PGND pin of the NCP3170. Drawing the real high power current flow lines on the recommended layout is important so the designer can see where the currents are flowing.

Figure 52. Recommended Signal Layout

The NCP3170 is the major source of power dissipation in the system for which the equations above detailed the loss mechanisms. The control portion of the IC power dissipation is determined by the formula below:

P C +I C V IN

(eq. 51)

I CC = Control circuitry current draw P C = Control power dissipation V IN

= Input voltage

Once the IC power dissipations are determined, the

designer can calculate the required thermal impedance to maintain a specified junction temperature at the worst case ambient temperature. The formula for calculating the junction temperature with the package in free air is:

T J +T A )P D R q JA

(eq. 52)

P D = Power dissipation of the IC

R q JA

= Thermal resistance junction to ambient of the regulator package

T A =

Ambient temperature T J = Junction temperature The thermal performance of the NCP3170 is strongly affected by the PCB layout. Extra care should be taken by users during the design process to ensure that the IC will operate under the recommended environmental conditions.As with any power design, proper laboratory testing should be performed to ensure the design will dissipate the required power under worst case operating conditions. Variables considered during testing should include maximum ambient

temperature, minimum airflow, maximum input voltage,maximum loading, and component variations (i.e., worst case MOSFET R DS(on)). Several layout tips are listed below for the best electric and thermal performance. Figure 53illustrates a PCB layout example of the NCP3170.

1.The VSW pin is connected to the internal PFET and NFET drains, which are a low resistance thermal path. Connect a large copper plane to the VSW pin to help thermal dissipation. If the PG pin is not used in the design, it can be connected to the VSW plane, further reducing the thermal

impedance. The designer should ensure that the VSW thermal plane is rounded at the corners to reduce noise.

2.The user should not use thermal relief connections to the VIN and the PGND pins. Construct a large plane around the PGND and VIN pins to help thermal dissipation.

3.The input capacitor should be connected to the VIN and PGND pins as close as possible to the IC.

4.A ground plane on the bottom and top layers of the PBC board is preferred. If a ground plane is not used, separate PGND from AGND and connect them only at one point to avoid the PGND pin noise coupling to the AGND pin.

5.Create copper planes as short as possible from the VSW pin to the output inductor, from the output inductor to the output capacitor, and from the load to PGND.

6.Create a copper plane on all of the unused PCB area and connect it to stable DC nodes such as:V IN , GND, or V OUT .

7.Keep sensitive signal traces far away from the VSW pins or shield them.

Figure 53. Recommend Thermal Layout

NCP3170

PACKAGE DIMENSIONS

SOIC −8 NB CASE 751−07ISSUE AK

NOTES:

1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 198

2.

2.CONTROLLING DIMENSION: MILLIMETER.

3.DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.

4.MAXIMUM MOLD PROTRUSION 0.15 (0.006)PER SIDE.

5.DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

6.751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−0

7.

DIM A MIN MAX MIN MAX INCHES

4.80

5.000.10.197MILLIMETERS B 3.80 4.000.1500.157C 1.35 1.750.0530.069D 0.330.510.0130.020G 1.27 BSC 0.050 BSC H 0.100.250.0040.010J 0.190.250.0070.010K 0.40 1.270.0160.050M 0 8 0 8 N 0.250.500.0100.020S

5.80

6.20

0.2280.244

M

Y

M

0.25 (0.010)

Y

M

0.25 (0.010)

Z S

X

S

____0.60.024ǒmm ǓSCALE 6:1

*For additional information on our Pb −Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

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