ADF4360-1[1]

ADF4360-1 Rev.B

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700www.analog.com Fax: 781.326.8703© 2004 Analog Devices, Inc. All rights reserved.

FEATURES

Output frequency range: 2050 MHz to 2450 MHz

Divide-by-2 output

3.0 V to 3.6 V power supply

1.8 V logic compatibility

Integer-N synthesizer

Programmable dual-modulus prescaler 8/9, 16/17, 32/33 Programmable output power level

3-wire serial interface

Analog and digital lock detect

Hardware and software power-down mode APPLICATIONS

Wireless handsets (DECT, GSM, PCS, DCS, WCDMA)

Test equipment

Wireless LANs

CATV equipment GENERAL DESCRIPTION

The ADF4360-1 is a fully integrated integer-N synthesizer and voltage-controlled oscillator (VCO). The ADF4360-1 is designed for a center frequency of 2250 MHz. In addition, there is a divide-by-2 option available, whereby the user gets an RF output of between 1025 MHz and 1225 MHz.

Control of all the on-chip registers is through a simple 3-wire interface. The device operates with a power supply ranging from 3.0 V to 3.6 V and can be powered down when not in use.

FUNCTIONAL BLOCK DIAGRAM

CP

VCO REF

TUNE

C C

C N

OUT A

OUT B

Figure 1.

ADF4360-1

Rev. B | Page 2 of 24

TABLE OF CONTENTS

Specifications.....................................................................................3 Timing Characteristics.....................................................................5 Absolute Maximum Ratings............................................................6 Transistor Count...........................................................................6 ESD Caution..................................................................................6 Pin Configuration and Function Descriptions.............................7 Typical Performance Characteristics.............................................8 Circuit Description...........................................................................9 Reference Input Section...............................................................9 Prescaler (P/P + 1)........................................................................9 A and B Counters.........................................................................9 R Counter......................................................................................9 PFD and Charge Pump................................................................9 MUXOUT and Lock Detect......................................................10 Input Shift Register.....................................................................10 VCO.............................................................................................10 Output Stage................................................................................11 Latch Structure...........................................................................12 Power-Up.....................................................................................16 Control Latch..............................................................................18 N Counter Latch.........................................................................19 R Counter Latch.........................................................................19 Applications.....................................................................................20 Direct Conversion Modulator..................................................20 Fixed Frequency LO...................................................................21 Interfacing...................................................................................21 PCB Design Guidelines for Chip-Scale Package..........................22 Output Matching........................................................................22 Outline Dimensions.......................................................................23 Ordering Guide.. (23)

REVISION HISTORY

12/04—Rev. A to Rev. B

Updated Format..................................................................Universal Changes to Specifications................................................................3 Changes to the Timing Characteristics.........................................5 Changes to the Power-Up Section................................................16 Added Table 10...............................................................................16 Added Figure 16..............................................................................16 Changes to Ordering Guide..........................................................23 Updated Outline Dimensions. (23)

6/04—Data Sheet Changed from Rev. 0 to Rev. A

Changes to Specifications................................................................3 Changes to Table 6..........................................................................12 Changes to Table 7..........................................................................13 Changes to Table 9.. (15)

8/03—Revision 0: Initial Version

ADF4360-1

Rev. B | Page 3 of 24

SPECIFICATIONS 1

AV DD = DV DD = V VCO = 3.3 V ± 10%; AGND = DGND = 0 V; T A = T MIN to T MAX , unless otherwise noted. Table 1.

Parameter B Version Unit Conditions/Comments REF IN CHARACTERISTICS REF IN Input Frequency 10/250 MHz min/max For f < 10 MHz, use a dc-coupled CMOS compatible

square wave, slew rate > 21 V/µs.

REF IN Input Sensitivity 0.7/AV DD p-p min/max AC-coupled. 0 to AV DD V max CMOS compatible. REF IN Input Capacitance 5.0 pF max REF IN Input Current ±100 µA max PHASE DETECTOR

Phase Detector Frequency 2

8 MHz max CHARGE PUMP

I CP Sink/Source 3

With R SET = 4.7 kΩ. High Value 2.5 mA typ Low Value 0.312 mA typ R SET Range 2.7/10 kΩ I CP 3-State Leakage Current 0.2 nA typ Sink and Source Current Matching 2 % typ 1.25 V ≤ V CP ≤ 2.5 V. I CP vs. V CP 1.5 % typ 1.25 V ≤ V CP ≤ 2.5 V. I CP vs. Temperature 2 % typ V CP = 2.0 V. LOGIC INPUTS V INH , Input High Voltage 1.5 V min V INL , Input Low Voltage 0.6 V max I INH /I INL , Input Current ±1 µA max C IN , Input Capacitance 3.0 pF max LOGIC OUTPUTS V OH , Output High Voltage DV DD – 0.4 V min CMOS output chosen. I OH , Output High Current 500 µA max V OL , Output Low Voltage 0.4 V max I OL = 500 µA. POWER SUPPLIES AV DD 3.0/3.6 V min/V max DV DD AV DD V VCO AV DD AI DD 410 mA typ

DI DD 4 2.5 mA typ I VCO 4, 524.0 mA typ I CORE = 15 mA.

I RFOUT 4

3.5 – 11.0 mA typ RF output stage is programmable.

Low Power Sleep Mode 4

7 µA typ RF OUTPUT CHARACTERISTICS 5 VCO Output Frequency 2050/2450 MHz min/max I CORE = 15 mA. VCO Sensitivity 57 MHz/V typ Lock Time 00 µs typ To within 10 Hz of final frequency. Frequency Pushing (Open Loop) 6 MHz/V typ Frequency Pulling (Open Loop) 15 kHz typ Into 2.00 VSWR load. Harmonic Content (Second) −20 dBc typ Harmonic Content (Third) −35 dBc typ

Output Power 5, 7

−13/−6 dBm typ Programmable in 3 dB steps. See Table 7. Output Power Variation ±3 dB typ For tuned loads, see the Output Matching section. VCO Tuning Range 1.25/2.5 V min/max

ADF4360-1

Rev. B | Page 4 of 24

Parameter B Version Unit Conditions/Comments

NOISE CHARACTERISTICS 1, 5

VCO Phase-Noise Performance 8 −110 dBc/Hz typ @ 100 kHz offset from carrier. −130 dBc/Hz typ @ 1 MHz offset from carrier. −141 dBc/Hz typ @ 3 MHz offset from carrier. −148 dBc/Hz typ @ 10 MHz offset from carrier.

Synthesizer Phase-Noise Floor 9

−172 dBc/Hz typ @ 25 kHz PFD frequency. −163 dBc/Hz typ @ 200 kHz PFD frequency. −147 dBc/Hz typ @ 8 MHz PFD frequency. In-Band Phase Noise 10, 11−81 dBc/Hz typ @ 1 kHz offset from carrier.

RMS Integrated Phase Error 12

0.72 Degrees typ 100 Hz to 100 kHz.

Spurious Signals due to PFD Frequency 11, 13

−70 dBc typ Level of Unlocked Signal with MTLD Enabled −38 dBm typ

1 Operating temperature range is –40°C to +85°C.

2

Guaranteed by design. Sample tested to ensure compliance. 3

I CP is internally modified to maintain constant-loop gain over the frequency range. 4

T A = 25°C; AV DD = DV DD = V VCO = 3.3 V; P = 32. 5

These characteristics are guaranteed for VCO Core Power = 15 mA. 6

Jumping from 2.05 GHz to 2.45 GHz. PFD frequency = 200 kHz; loop bandwidth = 10 kHz. 7

Using 50 Ω resistors to V VCO into a 50 Ω load. For tuned loads, see the section. Output Matching 8

The noise of the VCO is measured in open-loop conditions. 9

The synthesizer phase-noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value). 10

The phase noise is measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REF IN for the synthesizer; offset frequency = 1 kHz. 11

f REFIN = 10 MHz; f PFD = 200 kHz; N = 12500; Loop B/W = 10 kHz. 12

f REFIN = 10 MHz; f PFD = 1 MHz; N = 2400; Loop B/W = 25 kHz. 13

The spurious signals are measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REF IN for the synthesizer; f REFOUT = 10 MHz @ 0 dBm.

ADF4360-1

Rev. B | Page 5 of 24

TIMING CHARACTERISTICS 1

AV DD = DV DD = V VCO = 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; T A = T MIN to T MAX , unless otherwise noted. Table 2.

Parameter Limit at T MIN to T MAX (B Version) Unit Test Conditions/Comments t 1 20 ns min LE Setup Time

t 2 10 ns min DATA to CLOCK Setup Time t 3 10 ns min DATA to CLOCK Hold Time t 4 25 ns min CLOCK High Duration t 5 25 ns min CLOCK Low Duration t 6 10 ns min CLOCK to LE Setup Time t 7

20

ns min

LE Pulse Width

1

See the section for the recommended power-up procedure for this device.

Power-Up

CLOCK

DATA

LE

LE

Figure 2. Timing Diagram

ADF4360-1

Rev. B | Page 6 of 24

ABSOLUTE MAXIMUM RATINGS

T A = 25°C, unless otherwise noted. Table 3.

Parameter Rating AV DD to GND 1−0.3 V to +3.9 V AV DD to DV DD −0.3 V to +0.3 V V VCO to GND −0.3 V to +3.9 V V VCO to AV DD −0.3 V to +0.3 V Digital I/O Voltage to GND −0.3 V to V DD + 0.3 V Analog I/O Voltage to GND −0.3 V to V DD + 0.3 V

REF IN to GND −0.3 V to V DD + 0.3 V

Operating Temperature Range

Maximum Junction Temperature 150°C

CSP θJA Thermal Impedance

(Paddle Soldered) 50°C/W (Paddle Not Soldered) 88°C/W Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C

1

GND = AGND = DGND = 0 V.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress rat-ing only; functional operation of the device at these or any other conditions above those indicated in the operational sec-tions of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability. This device is a high performance RF integrated circuit with an ESD rating of <1 kV and it is ESD sensitive. Proper precautions should be taken for handling and assembly.

TRANSISTOR COUNT 12543 (CMOS) and 700 (Bipolar)

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate

on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy elec-trostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CPGND

AV DD AGND RF OUT A RF OUT B

V VCO

DATA

CLK

REF IN

DGND

C N

R SET V

T

U

N

E

A

G

N

D

A

G

N

D

A

G

N

D

A

G

N

D

C

C

C

P

C

E

A

G

N

D

D

V

D

D

M

U

X

O

U

T

L

E

4

4

1

4

-

3 Figure 3. Pin Configuration

TYPICAL PERFORMANCE CHARACTERISTICS

FREQUENCY OFFSET (Hz)

O U T P U T P O W E R (d B )

Figure 4. Open Loop VCO Phase Noise

04414-005

–145–150–155

–140–135–130–125–120–115–110–105–90–95–100–85–80–75–70100

10M

1M 100k

10k 1000

FREQUENCY OFFSET (Hz)

O U T P U T P O W E R (d B )

Figure 5. VCO Phase Noise, 2250 MHz, 200 kHz PFD, 10 kHz Loop Bandwidth

04414-006

–145–150–155

–140–135–130–125–120–115–110–105–90–95–100–85–80–75–70100

10M

1M 100k

10k 1000

FREQUENCY OFFSET (Hz)

O U T P U T P O W E R (d B )

Figure 6. VCO Phase Noise, 1125 MHz,

Divide-by-2 Enabled, 200 kHz PFD, 10 kHz Loop Bandwidth

O U T P U T P O W E R (d B )

–2kHz –1kHz 2250MHz 1kHz 2kHz

Figure 7. Close-In Phase Noise at 2250 MHz (200 kHz Channel Spacing)

O U T P U T P O W E R (d B )

–200kHz

–100kHz

2250MHz

100kHz

200kHz

Figure 8. Reference Spurs at 2250 MHz

(200 kHz Channel Spacing, 10 kHz Loop Bandwidth)

O U T P U T P O W E R (d B )

–90

–80

–70–60–50–40–30–20–100–1MHz

–0.5MHz

2250MHz

0.5MHz

1MHz

Figure 9. Reference Spurs at 2250 MHz

(1 MHz Channel Spacing, 25 kHz Loop Bandwidth)

CIRCUIT DESCRIPTION

REFERENCE INPUT SECTION

The reference input stage is shown in Figure 10. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed, and SW1 and SW2 are opened. This ensures that there is no loading of the REF IN pin on power-down.

04414-010

POWER-DOWN

Figure 10. Reference Input Stage

PRESCALER (P/P + 1)

The dual-modulus prescaler (P/P + 1), along with the A and B counters, enables the large division ratio, N , to be realized (N = BP + A). The dual-modulus prescaler, operating at CML levels, takes the clock from the VCO and divides it down to a manage-able frequency for the CMOS A and B counters. The prescaler is programmable. It can be set in software to 8/9, 16/17, or 32/33 and is based on a synchronous 4/5 core. There is a minimum divide ratio possible for fully contiguous output frequencies; this minimum is determined by P , the prescaler value, and is given by (P 2−P).

A AND

B COUNTERS

The A and B CMOS counters combine with the dual-modulus prescaler to allow a wide range division ratio in the PLL feed-back counter. The counters are specified to work when the prescaler output is 300 MHz or less. Thus, with a VCO

frequency of 2.5 GHz, a prescaler value of 16/17 is valid, but a value of 8/9 is not valid.

Pulse Swallow Function

The A and B counters, in conjunction with the dual-modulus prescaler, make it possible to generate output frequencies that are spaced only by the reference frequency divided by R. The VCO frequency equation is

()R f A B P f REFIN VCO /×]+×[=

where:

f VCO is the output frequency of the VCO.

P is the preset modulus of the dual-modulus prescaler (8/9, 16/17, and so on).

B is the preset divide ratio of the binary 13-bit counter (3 to 8191). A is the preset divide ratio of the binary 5-bit swallow counter (0 to 31). f REFIN is the external reference frequency oscillator.

Figure 11. A and B Counters

R COUNTER

The 14-bit R counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to 16,383 are allowed.

PFD AND CHARGE PUMP

The PFD takes inputs from the R counter and N counter

(N = BP + A) and produces an output proportional to the phase and frequency difference between them. Figure 12 is a simpli-fied schematic. The PFD includes a programmable delay ele-ment that controls the width of the antibacklash pulse. This pulse ensures that there is no dead zone in the PFD transfer function and minimizes phase noise and reference spurs. Two bits in the R counter latch, ABP2 and ABP1, control the width of the pulse (see Table 9).

04414-

01

2

Figure 12. PFD Simplified Schematic and Timing (In Lock)

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4360 family allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M3, M2, and M1 in the function latch. The full truth table is shown in Table 7. Figure 13 shows the MUXOUT section in block diagram form.

Lock Detect

MUXOUT can be programmed for two types of lock detect: digital and analog. Digital lock detect is active high. When LDP in the R counter latch is set to 0, digital lock detect is set high when the phase error on three consecutive phase detector cycles is less than 15 ns.

With LDP set to 1, five consecutive cycles of less than 15 ns phase error are required to set the lock detect. It stays set high until a phase error greater than 25 ns is detected on any subse-quent PD cycle.

The N-channel open-drain analog lock detect should be oper-ated with an external pull-up resistor of 10 kΩ nominal. When lock has been detected, the output will be high with narrow low-going pulses.

DGND

MUXOUT

DV ANALOG LOCK DETECT SDOUT

04414-013

Figure 13. MUXOUT Circuit

INPUT SHIFT REGISTER

The ADF4360 family’s digital section includes a 24-bit input shift register, a 14-bit R counter, and an 18-bit N counter, com-prising of a 5-bit A counter and a 13-bit B counter. Data is

clocked into the 24-bit shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the shift register to one of four latches on the rising edge of LE. The destination latch is determined by the state of the two control bits (C2, C1) in the shift register. The two LSBs are DB1 and DB0, as shown in Figure 2.

The truth table for these bits is shown in Table 5. Table 6 shows a summary of how the latches are programmed. Note that the test mode latch is used for factory testing and should not be programmed by the user.

Table 5. C2 and C1 Truth Table

Control Bits

C2 C1 Data Latch 0 0 Control Latch 0 1 R Counter

1 0 N Counter (A and B) 1

1

Test Mode Latch

VCO

The VCO core in the ADF4360 family uses eight overlapping bands, as shown in Figure 14, to allow a wide frequency range to be covered without a large VCO sensitivity (K V ) and resultant poor phase noise and spurious performance.

The correct band is chosen automatically by the band select logic at power-up or whenever the N counter latch is updated. It is important that the correct write sequence be followed at power-up. This sequence is 1. R counter latch 2. Control latch 3. N counter latch

During band select, which takes five PFD cycles, the VCO V TUNE is disconnected from the output of the loop filter and connected to an internal reference voltage.

04414-014

0.40.2

0.6

0.81.01.21.41.61.82.42.2

2.02.62.8

3.01850

1900

1950

2000

2050

2100

2150

2200

2250

2300

2350

2400

2450

2500

2550

2600

FREQUENCY (MHz)

V O L T A G E (V )

Figure 14. Frequency vs. V TUNE , ADF4360-1

The R counter output is used as the clock for the band select logic and should not exceed 1 MHz. A programmable divider is provided at the R counter input to allow division by 1, 2, 4, or 8 and is controlled by Bits BSC1 and BSC2 in the R counter latch. Where the required PFD frequency exceeds 1 MHz, the divide ratio should be set to allow enough time for correct band selection.

The operating current in the VCO core is programmable in four steps: 5 mA, 10 mA, 15 mA, and 20 mA. This is controlled by Bits PC1 and PC2 in the control latch.

OUTPUT STAGE

The RF OUT A and RF OUT B pins of the ADF4360 family are con-nected to the collectors of an NPN differential pair driven by buffered outputs of the VCO, as shown in Figure 15. To allow the user to optimize the power dissipation versus the output power requirements, the tail current of the differential pair is programmable via Bits PL1 and PL2 in the control latch. Four current levels may be set: 3.5 mA, 5 mA, 7.5 mA, and 11 mA. These levels give output power levels of −13 dBm, −10.5 dBm, −8 dBm, and −6 dBm, respectively, using a 50 Ω resistor to V DD and ac coupling into a 50 Ω load. Alternatively, both outputs can be combined in a 1 + 1:1 transformer or a 180° microstrip coupler (see the Output Matching section). If the outputs are used individually, the optimum output stage consists of a shunt inductor to V DD.

Another feature of the ADF4360 family is that the supply current to the RF output stage is shut down until the part achieves lock as measured by the digital lock detect circuitry. This is enabled by the mute-till-lock detect (MTLD) bit in the control latch.

RF A RF B

Figure 15. Output Stage ADF4360-1LATCH STRUCTURE

Table 6 shows the three on-chip latches for the ADF4360 family. The two LSBs determine which latch is programmed. Table 6. Latch Structure

CONTROL LATCH

N COUNTER LATCH

R COUNTER LATCH

Table 7. Control Latch

Table 9. R Counter Latch

POWER-UP

Power-Up Sequence

The correct programming sequence for the ADF4360-1 after power-up is: 1. R counter latch 2. Control latch 3. N counter latch

Initial Power-Up

Initial power-up refers to programming the part after the

application of voltage to the AV DD , DV DD , V VCO , and CE pins. On initial power-up, an interval is required between programming the control latch and programming the N counter latch. This interval is necessary to allow the transient behavior of the ADF4360-1 during initial power-up to have settled.

During initial power-up, a write to the control latch powers up the part and the bias currents of the VCO begin to settle. If these currents have not settled to within 10% of their steady-state value, and if the N counter latch is then programmed, the VCO may not oscillate at the desired frequency, which does not allow the band select logic to choose the correct frequency band and the ADF4360-1 may not achieve lock. If the recommended interval is inserted, and the N counter latch is programmed, the band select logic can choose the correct frequency band, and the part locks to the correct frequency.

The duration of this interval is affected by the value of the capacitor on the C N pin (Pin 14). This capacitor is used to reduce the close-in noise of the ADF4360-1 VCO. The recom-mended value of this capacitor is 10 µF. Using this value requires an interval of ≥ 5 ms between the latching in of the control latch bits and latching in of the N counter latch bits. If a shorter delay is required, this capacitor can be reduced. A slight phase noise penalty is incurred by this change, which is explained in the Table 10.

Table 10. C N Capacitance vs. Interval and Phase Noise

C N Value Recommended Interval between Control Latch and N Counter Latch Open-Loop Phase Noise @ 10 kHz Offset 10 µF ≥ 5 ms −85 dBc 440 nF

≥ 600 µs

−84 dBc

CLOCK

POWER-UP

DATA

LE

CONTROL LATCH WRITE TO N COUNTER LATCH WRITE

04414-02

Figure 16. ADF4360-1 Power-Up Timing

If the ADF4360-1 is powered down via the hardware (using the CE pin) and powered up again without any change to the N counter register during power-down, it locks at the correct fre-quency because the part is already in the correct frequency band. The lock time depends on the value of capacitance on the C N pin, which is <5 ms for 10 µF capacitance. The smaller ca-pacitance of 440 nF on this pin enables lock times of <600 µs. The N counter value cannot be changed while the part is in power-down because it may not lock to the correct frequency on power-up. If it is updated, the correct programming se-quence for the part after power-up is to the R counter latch, followed by the control latch, and finally the N counter latch, with the required interval between the control latch and N counter latch, as described in the Initial Power-Up section. Software Power-Up/Power-Down

If the ADF4360-1 is powered down via the software (using the control latch) and powered up again without any change to the N counter latch during power-down, it locks at the correct fre-quency because it is already in the correct frequency band. The lock time depends on the value of capacitance on the C N pin, which is <5 ms for 10 µF capacitance. The smaller capacitance of 440 nF on this pin enables lock times of <600 µs.

The N counter value cannot be changed while the part is in power-down because it may not lock to the correct frequency on power-up. If it is updated, the correct programming se-quence for the part after power-up is to the R counter latch, followed by the control latch, and finally the N counter latch, with the required interval between the control latch and N counter latch, as described in the Initial Power-Up section.CONTROL LATCH

With (C2, C1) = (0, 0), the control latch is programmed. Table 7 shows the input data format for programming the control latch. Prescaler Value

In the ADF4360 family, P2 and P1 in the control latch set the prescaler values.

Power-Down

DB21 (PD2) and DB20 (PD1) provide programmable power-down modes.

In the programmed asynchronous power-down, the device powers down immediately after latching a 1 into Bit PD1, with the condition that PD2 has been loaded with a 0. In the pro-grammed synchronous power-down, the device power-down is gated by the charge pump to prevent unwanted frequency jumps. Once the power-down is enabled by writing a 1 into

Bit PD1 (on the condition that a 1 has also been loaded to PD2), the device will go into power-down on the second rising edge of the R counter output, after LE goes high. When the CE pin is low, the device is immediately disabled regardless of the state of PD1 or PD2.

When a power-down is activated (either in synchronous or asynchronous mode), the following events occur:

•All active dc current paths are removed.

•The R, N, and timeout counters are forced to their load state conditions.

•The charge pump is forced into three-state mode.

•The digital lock detect circuitry is reset.

•The RF outputs are debiased to a high impedance state. •The reference input buffer circuitry is disabled.

•The input register remains active and capable of loading and latching data. Charge Pump Currents

CPI3, CPI2, and CPI1 in the ADF4360 family determine Current Setting 1.

CPI6, CPI5, and CPI4 determine Current Setting 2. See the truth table in Table 7.

Output Power Level

Bits PL1 and PL2 set the output power level of the VCO. See the truth table in Table 7.

Mute-Till-Lock Detect

DB11 of the control latch in the ADF4360 family is the mute-till-lock detect bit. This function, when enabled, ensures that the RF outputs are not switched on until the PLL is locked.

CP Gain

DB10 of the control latch in the ADF4360 family is the charge pump gain bit. When it is programmed to a 1, Current Setting 2 is used. When it is programmed to a 0, Current Setting 1 is used. Charge Pump Three-State

This bit puts the charge pump into three-state mode when programmed to a 1. It should be set to 0 for normal operation. Phase Detector Polarity

The PDP bit in the ADF4360 family sets the phase detector polarity. The positive setting enabled by programming a 1 is used when using the on-chip VCO with a passive loop filter or with an active noninverting filter. It can also be set to 0. This is required if an active inverting loop filter is used.

MUXOUT Control

The on-chip multiplexer is controlled by M3, M2, and M1.

See the truth table in Table 7.

Counter Reset

DB4 is the counter reset bit for the ADF4360 family. When this is 1, the R counter and the A, B counters are reset. For normal operation, this bit should be 0.

Core Power Level

PC1 and PC2 set the power level in the VCO core. The recom-mended setting is 15 mA. See the truth table in Table 7.

N COUNTER LATCH

With (C2, C1) = (1, 0), the N counter latch is programmed. Table 8 shows the input data format for programming the

N counter latch.

A Counter Latch

A5 to A1 program the 5-bit A counter. The divide range is 0 (00000) to 31 (11111).

Reserved Bits

DB7 is a spare bit that is reserved. It should be programmed to 0.

B Counter Latch

B13 to B1 program the B counter. The divide range is 3 (00.....0011) to 8191 (11....111).

Overall Divide Range

The overall divide range is defined by ((P × B) + A), where P is the prescaler value.

CP Gain

DB21 of the N counter latch in the ADF4360 family is the charge pump gain bit. When this is programmed to 1, Current Setting 2 is used. When programmed to 0, Current Setting 1 is used. This bit can also be programmed through DB10 of the control latch. The bit will always reflect the latest value written to it, whether this is through the control latch or the N counter latch. Divide-by-2

DB22 is the divide-by-2 bit. When set to 1, the output divide-by-2 function is chosen. When it is set to 0, normal operation occurs. Divide-by-2 Select

DB23 is the divide-by-2 select bit. When programmed to 1, the divide-by-2 output is selected as the prescaler input. When set to 0, the fundamental is used as the prescaler input. For exam-ple, using the output divide-by-2 feature and a PFD frequency of 200 kHz, the user will need a value of N = 12,000 to generate 1.2 GHz. With the divide-by-2 select bit high, the user may keep N = 6,000. R COUNTER LATCH

With (C2, C1) = (0, 1), the R counter latch is programmed. Table 9 shows the input data format for programming the

R counter latch.

R Counter

R1 to R14 set the counter divide ratio. The divide range is 1 (00......001) to 16383 (111......111).

Antibacklash Pulse Width

DB16 and DB17 set the antibacklash pulse width.

Lock Detect Precision

DB18 is the lock detect precision bit and sets the number of reference cycles with less than 15 ns phase error for entering the locked state. With LDP at 1, five cycles are taken, and with LDP at 0, three cycles are taken.

Test Mode Bit

DB19 is the test mode bit (TMB) and should be set to 0. With TMB = 0, the contents of the test mode latch are ignored and normal operation occurs as determined by the contents of the control latch, R counter latch, and N counter latch. Note that test modes are for factory testing only and should not be pro-grammed by the user.

Band Select Clock

These bits set a divider for the band select logic clock input. The output of the R counter is by default the value used to clock the band select logic, but if this value is too high (>1 MHz), a divider can be switched on to divide the R counter output to a smaller value (see Table 9).

Reserved Bits

DB23 to DB22 are spare bits that are reserved. They should be programmed to 0.APPLICATIONS

DIRECT CONVERSION MODULATOR

Direct conversion architectures are increasingly being used to implement base station transmitters. Figure 17 shows how ADI parts can be used to implement such a system.

The circuit block diagram shows the AD9761 TxDAC® being used with the AD8349. The use of dual integrated DACs, such as the AD9761 with its specified ±0.02 dB and ±0.004 dB gain and offset matching characteristics, ensures minimum error contribution (over temperature) from this portion of the signal chain.

The local oscillator is implemented using the ADF4360-1. The low-pass filter was designed using ADIsimPLL for a channel spacing of 1 MHz and an open-loop bandwidth of 25 kHz. The frequency range of the ADF4360-1 (2.05 GHz to 2.45 GHz) makes it ideally suited for implementation of a Bluetooth® transceiver. The LO ports of the AD8349 can be driven differentially from the complementary RF OUT A and RF OUT B outputs of the

ADF4360-1. This gives a better performance than a single-ended LO driver and eliminates the often necessary use of a balun to convert from a single-ended LO input to the more desirable differential LO inputs for the AD8349. The typical rms phase noise (100 Hz to 100 kHz) of the LO in this configuration is 1.09°.

The AD8349 accepts LO drive levels from −10 dBm to 0 dBm. The optimum LO power can be software programmed on the ADF4360-1, which allows levels from −13 dBm to −6 dBm from each output.

The RF output is designed to drive a 50 Ω load but must be

ac-coupled, as shown in Figure 17. If the I and Q inputs are driven in quadrature by 2 V p-p signals, the resulting output power from the modulator will be approximately 2 dBm.

Figure 17. Direct Conversion Modulator

FIXED FREQUENCY LO

Figure 18 shows the ADF4360-1 used as a fixed frequency LO at 2.2 GHz. The low-pass filter was designed using ADIsimPLL for a channel spacing of 8 MHz and an open-loop bandwidth of 40 kHz. The maximum PFD frequency of the ADF4360-1 is 8 MHz. Because using a larger PFD frequency allows users to use a smaller N, the in-band phase noise is reduced to as low as possible, –99 dBc/Hz. The 40 kHz bandwidth is chosen to be just greater than the point at which the open-loop phase noise of the VCO is –99 dBc/Hz, thus giving the best possible inte-grated noise. The typical rms phase noise (100 Hz to 100 kHz) of the LO in this configuration is 0.3°. The reference frequency is from a 16 MHz TCXO from Fox, thus an R value of 2 is pro-grammed. Taking into account the high PFD frequency and its effect on the band select logic, the band select clock divider is enabled. In this case, a value of 8 is chosen. A very simple pull-up resistor and dc blocking capacitor complete the RF output stage.

LOCK

Figure 18. Fixed Frequency LO

INTERFACING

The ADF4360 family has a simple SPI®-compatible serial inter-face for writing to the device. CLK, DATA, and LE control the data transfer. When LE goes high, the 24 bits that are clocked into the appropriate register on each rising edge of CLK get transferred to the appropriate latch. See Figure 2 for the timing diagram and Table 5 for the latch truth table.

The maximum allowable serial clock rate is 20 MHz. This means the maximum update rate possible is 833 kHz or one update every 1.2 µs. This is certainly more than adequate for systems that will have typical lock times in hundreds of micro-seconds.

ADuC812 Interface

Figure 19 shows the interface between the ADF4360 family and the ADuC812 MicroConverter®. Because the ADuC812 is based on an 8051 core, this interface can be used with any 8051 based microcontroller. The MicroConverter is set up for SPI master mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF4360 family needs a 24-bit word, which is accomplished by writing three 8-bit bytes from the MicroConverter to the device. When the third byte is written, the LE input should be brought high to complete the transfer.

Figure 19. ADuC812 to ADF4360-x Interface

I/O port lines on the ADuC812 are also used to control power-down (CE input) and detect lock (MUXOUT configured as lock detect and polled by the port input). When operating in the described mode, the maximum SCLOCK rate of the ADuC812 is 4 MHz. This means that the maximum rate at which the out-put frequency can be changed is 166 kHz.

ADSP-21xx Interface

Figure 20 shows the interface between the ADF4360 family and the ADSP-21xx digital signal processor. The ADF4360 family needs a 24-bit serial word for each latch write. The easiest way to accomplish this using the ADSP-21xx family is to use the autobuffered transmit mode of operation with alternate fram-ing. This provides a means for transmitting an entire block of serial data before an interrupt is generated.

Figure 20. ADSP-21xx to ADF4360-x Interface

Set up the word length for 8 bits and use three memory loca-tions for each 24-bit word. To program each 24-bit latch, store the 8-bit bytes, enable the autobuffered mode, and write to the transmit register of the DSP . This last operation initiates the autobuffer transfer.

PCB DESIGN GUIDELINES FOR CHIP-SCALE PACKAGE

The leads on the chip-scale package (CP-24) are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package lead length and 0.05 mm wider than the package lead width. The lead should be centered on the pad to ensure that the solder joint size is maximized.

The bottom of the chip-scale package has a central thermal pad. The thermal pad on the printed circuit board should be at least as large as this exposed pad. On the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern to ensure that short-ing is avoided.

Thermal vias may be used on the printed circuit board thermal pad to improve thermal performance of the package. If vias are used, they should be incorporated in the thermal pad at a

1.2 mm pitch grid. The via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 ounce of copper to plug the via.

The user should connect the printed circuit thermal pad to AGND. This is internally connected to AGND.

OUTPUT MATCHING

There are a number of ways to match the output of the

ADF4360-1 for optimum operation; the most basic is to use a 50 Ω resistor to V VCO . A dc bypass capacitor of 100 pF is con-nected in series, as shown Figure 21. Because the resistor is not frequency dependent, this provides a good broadband match. The output power in this circuit typically gives −6 dBm output power into a 50 Ω load.

04414-025

RF OUT

V VCO

Ω

Figure 21. Simple ADF4360-1 Output Stage

A better solution is to use a shunt inductor (acting as an RF choke) to V VCO . This gives a better match and hence more output power. Additionally, a series inductor is added after the dc bypass capacitor to provide a resonant LC circuit. This tunes the oscillator output and provides approximately 10 d

B addi-tional rejection of the second harmonic. The shunt inductor needs to be a relatively high value (>40 nH). Experiments have shown that Figure 22 provides an excellent match to 50 Ω over the operating range of the ADF4360-1. This gives approximately −4 dBm output power across the frequency range of the ADF4360-1. Both single-ended architectures can be examined using the EV AL_ADF4360-1EB1 evaluation board.

04414-026

RF V Ω

Figure 22. Optimum ADF4360-1 Output Stage

If the user does not need the differential outputs available on the ADF4360-1, the user may either terminate the unused out-put or combine both outputs using a balun. The circuit in Figure 23 shows how best to combine the outputs.

Ω

RF OUT V RF OUT 04414-027

Figure 23. Balun for Combining ADF4360-1 RF Outputs

The circuit in Figure 23 is a lumped-lattice-type LC balun. It is designed for a center frequency of 2.2 GHz and outputs 1.0 dBm at this frequency. The series 1 nH inductor is used to tune out any parasitic capacitance due to the board layout from each input, and the remainder of the circuit is used to shift the output of one RF input by +90° and the second by −90°, thus combining the two. The action of the 3.6 nH inductor and the 1.5 pF capacitor accomplish this. The 47 nH is used to provide an RF choke in order to feed the supply voltage, and the 10 pF capacitor provides the necessary dc block. To ensure good RF performance, the circuits in Figure 22 and Figure 23 were im-plemented with Coilcraft 0402/0603 inductors and AVX 0402 thin-film capacitors.

Alternatively, instead of the LC balun shown in Figure 23, both outputs may be combined using a 180° rat-race coupler.

*COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2

EXCEPT FOR EXPOSED PAD DIMENSION

Figure 24. 24-Lead Lead Frame Chip-Scale Package [VQ_LFCSP]

4 mm × 4 mm Body, Very Thin Quad (CP-24-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Frequency Range Package Option

ADF4360-1BCP −40°C to +85°C 2050 MHz to 2450 MHz CP-24-2

ADF4360-1BCPRL −40°C to +85°C 2050 MHz to 2450 MHz CP-24-2

ADF4360-1BCPRL7 −40°C to +85°C 2050 MHz to 2450 MHz CP-24-2

ADF4360-1BCPZ1−40°C to +85°C 2050 MHz to 2450 MHz CP-24-2

ADF4360-1BCPZRL1−40°C to +85°C 2050 MHz to 2450 MHz CP-24-2

ADF4360-1BCPZRL71−40°C to +85°C 2050 MHz to 2450 MHz CP-24-2

Board EVAL-ADF4360-1EB1 Evaluation

1 Z = Pb-free part.NOTES

Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.

C04414–0–12/04(B)