VHDL波形发生器

目的：利用VHDL语言为编程工具，以ALTEAR的FPGA芯片为编程对象，以QUARTUS II为EDA开发软件平台，设计具有一定复杂度实用系统。主要目的是使学生初步了解软件设计相关知识及步骤、进一步理解TOP——DOWN设计思想、更全面地掌握VHDL语言相关知识、了解实用程序的调试方法。

系统功能介绍及总体结构设计

（1）功能介绍：

函数发生器由波形选择开关控制波形的输出，分别能输出方波、阶梯波、锯齿波递减和锯齿波递增、三角波、正弦波六种波形，考虑程序的容量，每种波形在一个周期内均取32个取样点。本设计采用自顶向下的设计方法进行设计。clock为系统时钟，clr为系统清零信号，fpxs为分频器的分频系数，s是波形选择开关，系统获得的数字信号经D/A转换器即可转换成模拟信号输出波形。

（2）总体结构设计：如下图带分频功能的函数发生器系统图1

LIBRARY IEEE;--选择器

USE IEEE.STD_LOGIC_11.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY Xuanzeqi IS

PORT (  sel: in std_logic_vector(2 downto 0);

    d1,d2,d3,d4,d5,d6:in std_logic_vector(7 downto 0);

    q:out std_logic_vector(7 downto 0));

END ENTITY Xuanzeqi;

ARCHITECTURE behave OF Xuanzeqi IS

BEGIN

PROCESS(sel)

BEGIN

CASE sel IS

WHEN "001"=>q<=d1;--方波

WHEN "010"=>q<=d2;--阶梯波

WHEN "011"=>q<=d3;--锯齿波递减

WHEN "100"=>q<=d4;--锯齿波递增

WHEN "101"=>q<=d5;--三角波

WHEN "110"=>q<=d6;--正弦波

WHEN OTHERS=>null;

END CASE;

END PROCESS;

END ARCHITECTURE behave;

LIBRARY IEEE;--方波

USE IEEE.STD_LOGIC_11.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY Fangbo IS

 PORT ( clk,reset:in std_logic;

    q: out std_logic_vector(7 DOWNTO 0));

END ENTITY Fangbo;

ARCHITECTURE behave OF Fangbo IS

SIGNAL temp : std_logic ;

BEGIN

    PROCESS(clk,reset)

    VARIABLE tmp: std_logic_vector(7 downto 0);

 BEGIN

    IF reset='0' THEN

temp<='0';

    ELSIF rising_edge(clk) THEN

          IF tmp="11111111" THEN

                 tmp:="00000000";

          ELSE

                 tmp:=tmp+1;

          END IF;

     IF tmp<="10000000" THEN

        temp<='1';

        ELSE

       temp<='0';

        END IF;

    END IF;

END PROCESS;

PROCESS(clk,temp)

BEGIN

    IF rising_edge(clk) THEN

         IF temp='1' THEN

       q<="01111111"; --占空比？

         ELSE

        q<="00000000";

         END IF;

    END IF;

END PROCESS;

END ARCHITECTURE behave;

LIBRARY IEEE;--阶梯波

USE IEEE.STD_LOGIC_11.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY Jietibo IS

PORT (  clk,reset:in std_logic;

    q:out std_logic_vector(7 downto 0));

END ENTITY Jietibo;

ARCHITECTURE behave OF Jietibo IS

BEGIN

    PROCESS(clk,reset)

      VARIABLE tmp: std_logic_vector(7 downto 0);

    BEGIN

       IF reset='0' THEN

        tmp:="00000000";

       ELSIF rising_edge(clk) THEN

         IF tmp="11111111" THEN

                   tmp:="00000000";

         ELSE

               tmp:=tmp+6;--阶梯为6？

         END IF;

       END IF;

     q<=tmp;

END PROCESS;

END ARCHITECTURE behave;

LIBRARY IEEE;--锯齿波递减

USE IEEE.STD_LOGIC_11.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY Juchibo_dijian IS

PORT (  clk,reset:in std_logic;

     q:out std_logic_vector(7 downto 0));

END ENTITY Juchibo_dijian;

ARCHITECTURE behave OF Juchibo_dijian IS

BEGIN

    PROCESS(clk,reset)

       VARIABLE tmp: std_logic_vector(7 downto 0);

    BEGIN 

       IF reset='0' THEN

         tmp:="11111111";

       ELSIF rising_edge(clk) THEN

        IF tmp="00000000" THEN

                tmp:="11111111";

        ELSE

             tmp:=tmp-1; --阶梯为1

        END IF;

       END IF;

q<=tmp;

END PROCESS;

END ARCHITECTURE behave;

LIBRARY IEEE;--锯齿波递增

USE IEEE.STD_LOGIC_11.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY Juchibo_dizeng IS

PORT (   clk,reset:in std_logic;

      q:out std_logic_vector(7 downto 0));

END ENTITY Juchibo_dizeng;

ARCHITECTURE behave OF Juchibo_dizeng IS

BEGIN

     PROCESS(clk,reset)

       VARIABLE tmp: std_logic_vector(7 downto 0);

        BEGIN 

        IF reset='0' THEN

             tmp:="00000000";

        ELSIF rising_edge(clk) THEN

            IF tmp="11111111" THEN

                    tmp:="00000000";

            ELSE

                 tmp:=tmp+1;

            END IF;

        END IF;

q<=tmp;

END PROCESS;

END ARCHITECTURE behave;

LIBRARY IEEE;--三角波

USE IEEE.STD_LOGIC_11.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY Sanjiaobo IS

PORT (   clk,reset:in std_logic;

      q:out std_logic_vector(7 downto 0));

END ENTITY Sanjiaobo;

ARCHITECTURE behave OF Sanjiaobo IS

BEGIN

    PROCESS(clk,reset)

       VARIABLE temp1:std_logic_vector(7 downto 0);

       VARIABLE temp2:std_logic;

          BEGIN

        IF reset='0' THEN

           temp1:="00000000";

        ELSIF rising_edge(clk) THEN

             IF temp2='0' THEN

              IF  temp1="11111110" THEN

                  temp1:="11111111" ;

                  temp2:='1';

              ELSE

                  temp1:=temp1+1;

              END IF;

           ELSE

              IF temp1="00000001" THEN

                    temp1:="00000000";

                   temp2:='0';

              ELSE

                    temp1:=temp1-1;

              END IF;

           END IF;

        END IF;

q<=temp1;

END PROCESS;

END ARCHITECTURE behave;

library ieee;--正弦波

use ieee.std_logic_11.all;

use ieee.std_logic_unsigned.all;

entity Zhengxianbo is

port (clk,reset :in std_logic;--clock时钟信号，clrn复位信号

    qt: out std_logic_vector(7 downto 0)); --8位数据输出

end  Zhengxianbo;

architecture behave of  Zhengxianbo is

signal q: std_logic_vector(8 downto 0);

begin

process(clk,reset)

 variable tmp : integer range  downto 0;

begin

if reset='0' then q<="000000000";tmp:=0;

 elsif clk'event and clk='1' then

    if tmp= then  tmp:=0;else tmp:=tmp+1;end if;

    case tmp is

when 0 =>q<="000000000";when 1 =>q<="000011001";when 2 =>q<="000110010";when 3 =>q<="001001010";

when 4 =>q<="001100010";when 5 =>q<="001111000";when 6 =>q<="010001110";when 7 =>q<="010100010";

when 8 =>q<="010110100";when 9 =>q<="011000101";when 10 =>q<="011010100";when 11 =>q<="011100001";

when 12 =>q<="011101110";when 13 =>q<="011110100";when 14 =>q<="011111010";when 15 =>q<="011111110";

when 16 =>q<="011111111";when 17 =>q<="011111110";when 18 =>q<="011111010";when 19 =>q<="011110100";                                             

when 20 =>q<="011101110";when 21 =>q<="011100001";when 22 =>q<="011010100";when 23 =>q<="011000101";

when 24 =>q<="010110100";when 25 =>q<="010100010";when 26 =>q<="010001110";when 27 =>q<="001111000";

when 28 =>q<="001100010";when 29 =>q<="001001010";when 30 =>q<="000110010";when 31 =>q<="000011001";

when 32 =>q<="000000000";when 33 =>q<="111100111";when 34 =>q<="111001110";when 35 =>q<="110110110";

when 36 =>q<="110011110";when 37 =>q<="110000111";when 38 =>q<="101011110";when 39 =>q<="101001110";

when 40 =>q<="101001100";when 41 =>q<="100111011";when 42 =>q<="100101100";when 43 =>q<="100011111";

when 44 =>q<="100010010";when 45 =>q<="100001100";when 46 =>q<="100000110";when 47 =>q<="100000010";

when 48 =>q<="100000001";when 49 =>q<="100000010";when 50 =>q<="100000110";when 51 =>q<="100001100";

when 52 =>q<="100010010";when 53 =>q<="100011111";when 54 =>q<="100101100";when 55 =>q<="100111011";

when 56 =>q<="101001100";when 57 =>q<="101011110";when 58 =>q<="101011010";when 59 =>q<="101100111";

when 60 =>q<="101110000";when 61 =>q<="110000000";when 62 =>q<="110001110";when 63 =>q<="110010111";

when =>q<="000000000";

when others =>NULL;

    end case;

    end if;

qt<=q(8 downto 1);

  end process;

end behave;

LIBRARY IEEE;--函数发生器

USE IEEE.STD_LOGIC_11.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY Hanshufashengqi_6 IS

PORT (  clock:in std_logic;

    clr:IN STD_LOGIC;

    s:IN STD_LOGIC_VECTOR ( 2 DOWNTO 0);

    qq:OUT STD_LOGIC_VECTOR (7 DOWNTO 0));

END ENTITY Hanshufashengqi_6;

ARCHITECTURE behave of Hanshufashengqi_6 IS

component Xuanzeqi

PORT (  sel:IN STD_LOGIC_VECTOR ( 2 DOWNTO 0);

    d6,d5,d4,d3, d2, d1: IN STD_LOGIC_VECTOR ( 7 DOWNTO 0);

    q:OUT STD_LOGIC_VECTOR (7 DOWNTO 0));

END component Xuanzeqi;

component Fangbo 

port ( clk,reset:in std_logic;

    q: out std_logic_vector(7 downto 0));

end component Fangbo;

component Jietibo

port ( clk,reset:in std_logic;

    q: out std_logic_vector(7 downto 0));

end component Jietibo;

component Juchibo_dijian 

port ( clk,reset:in std_logic;

    q: out std_logic_vector(7 downto 0));

end component Juchibo_dijian;

component Juchibo_dizeng 

port ( clk,reset:in std_logic;

    q: out std_logic_vector(7 downto 0));

end component Juchibo_dizeng;

component Sanjiaobo

port (clk,reset:in std_logic;

    q: out std_logic_vector(7 downto 0));

end component Sanjiaobo;

component Zhengxianbo

port (clk,reset:in std_logic;

    qt: out std_logic_vector(7 downto 0));

end component Zhengxianbo;

SIGNAL t1, t2, t3, t4, t5,t6: std_logic_vector ( 7 downto 0);

begin

u0: xuanzeqi port map ( sel =>s, q =>qq, d1 =>t1,

d2=>t2, d3=>t3, d4=>t4,d5=>t5,d6=>t6) ;

u1: Fangbo port map ( clk =>clock, reset =>clr,q=>t1);

u2: Jietibo port map ( clk =>clock, reset =>clr,q=>t2);

u3: Juchibo_dijian port map ( clk =>clock, reset =>clr, q =>t3);

u4: Juchibo_dizeng port map ( clk =>clock, reset=>clr, q =>t4);

u5: Sanjiaobo port map ( clk =>clock, reset=>clr, q =>t5);

u6: Zhengxianbo port map ( clk =>clock, reset=>clr, qt =>t6);

end behave;

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