电子钟 (FPGA设计verilog代码)

//电子钟：24小时制时分秒

//

//作者：yotain

//

//clk 50M时钟 CP 1Hz输出 可接LED指示灯

//nCR 清零（必须接 低电平异步清零）

//Adj_Min （分校正 低电平计时 必须接）

//Adj_Hour （时校正 低电平计时 必须接）

//dataout （数码管输出）

//en （数码管使能端）

//(Hour Minute Second 可以不接 也可以单独接数码管一位的)

//修改bcd_decoder 即可修改显示

//

//*****************************************

//************ timeclock top block*************

module top_clock ( Hour, Minute, Second, CP, nCR, EN, Adj_Min, Adj_Hour,clk,dataout,en) ;

input clk, nCR, EN, Adj_Min, Adj_Hour;

output CP;

output [7:0] Hour, Minute, Second,dataout;

output [3:0] en;

wire[7:0]Hour, Minute, Second, dataout;

supply1 Vdd;

wireMinL_EN, MinH_EN, Hour_EN;

//**************Hour, Minute, Second counter************

counter10 U1 ( Second[3:0], nCR, EN, CP);

counter6 U2 ( Second[7:4], nCR, ( Second[3:0]==4'h9), CP);

assign MinL_EN = Adj_Min? Vdd : (Second==8'h59);

assign MinH_EN = ( Adj_Min &&( Minute [3:0] ==4'h59))

|| ( Minute[3:0]==4'h9)&& (Second == 8'h59);

counter10 U3 ( Minute[3:0], nCR, MinL_EN,CP);

counter6U4 ( Minute[7:4], nCR, MinH_EN,CP);

assign Hour_EN = Adj_Hour ? Vdd: ((Minute == 8'h59)&&(Second == 8'h59));

counter24 U5 ( Hour[7:4], Hour[3:0], nCR, Hour_EN,CP);

bcd_decoder U6 (clk,nCR,Hour[7:4],Hour[3:0],Minute[7:4],Minute[3:0],dataout,en);

PULSE U7(clk,CP);

endmodule

//**************counter10 ( BCD 0~9 )*************

module counter10 ( Q, nCR, EN, CP);

inputCP, nCR, EN;

output[3 : 0]Q;

reg[3 : 0]Q;

always @ (posedge CP or negedge nCR)

begin

if( !nCR ) Q<=4'b0000;

else if ( !EN ) Q<=Q;

else if ( Q ==4'b1001) Q <= 4'b0000;

else Q <= Q+1'b1;

end

endmodule

//**************counter6 ( BCD 0~5 )************

module counter6 ( Q, nCR, EN, CP);

input CP, nCR, EN;

output[3:0]Q;

reg[3:0]Q;

always @ (posedge CP or negedge nCR )

begin

if(!nCR)Q<=4'b0000;

else if (!EN)Q<=Q;

else if (Q == 4'b0101) Q<=4'b0000;

else Q <= Q + 1'b1;

end

endmodule

//***************counter24 ( 0~23 )**************

module counter24 ( CntH, CntL, nCR, EN, CP);

input CP, nCR, EN;

output[3:0]CntH,CntL;

reg [3:0]CntH,CntL;

reg CO;

always @ (posedge CP or negedge nCR)

begin

if(!nCR){CntH,CntL} <=8'h00;

else if(!EN){CntH,CntL} <= {CntH,CntL};

else if ( (CntH>2)||(CntL>9) || ( (CntH==2)&&(CntL>=3) ) )

{CntH,CntL} <=8'h00;

else if((CntH==2)&&(CntL<3))

begin

CntH<=CntH;

CntL<=CntL+1'b1;

end

else if (CntL==9)

begin

CntH=CntH+1'b1;

CntL=4'b0000;

end

else begin

CntH<=CntH;

CntL<=CntL+1'b1;

end

end

endmodule

//*************cnt_1Hz*****************

module PULSE ( clk, clk_1Hz);

input clk;

output clk_1Hz;

reg[24:0]cnt_1Hz;

reg R_clk=0;

assign clk_1Hz=R_clk;

always @ (posedge clk)

begin

if (cnt_1Hz==50000000) cnt_1Hz<=0;

else cnt_1Hz<=cnt_1Hz+1;

end

always @ (posedge clk)

begin

if(cnt_1Hz<=25000000) R_clk<=1;

else R_clk<=0;

end

endmodule

//*************bcd_decoder*************

module bcd_decoder (clk,nCR,A,B,C,D,dataout,en);

input clk;//system clock

input nCR;//system reset,low is active

input [3:0] A,B,C,D;

output[7:0] dataout;

output[3:0] en;//enable high is active

reg[7:0] dataout;

reg[4:0] en;

reg[15:0] cnt_scan;

reg[3:0] dataout_buf;

always@(posedge clk or negedge nCR)

begin

if(!nCR) begin

cnt_scan<=0;

end

else begin

cnt_scan<=cnt_scan+1;

end

end

always@(cnt_scan)

begin

case(cnt_scan[15:14])

2'b00:

en=4'b0001;

2'b01:

en=4'b0010;

2'b10:

en=4'b0100;

2'b11:

en=4'b1000;

default:

en=4'b1111;

endcase

end

always@(en)

begin

case(en)

4'b0001:

dataout_buf=A;

4'b0010:

dataout_buf=B;

4'b0100:

dataout_buf=C;

4'b1000:

dataout_buf=D;

default:

dataout_buf=4'b0000;

endcase

end

always@(dataout_buf)

begin

case(dataout_buf)

4'b0000:

dataout=8'b1111_1100;

4'b0001:

dataout=8'b0110_0000;

4'b0010:

dataout=8'b1101_1010;

4'b0011:

dataout=8'b1111_0010;

4'b0100:

dataout=8'b0110_0110;

4'b0101:

dataout=8'b1011_0110;

4'b0110:

dataout=8'b1011_1110;

4'b0111:

dataout=8'b1110_0000;

4'b1000:

dataout=8'b1111_1110;

4'b1001:

dataout=8'b1110_0110;

4'b1010:

dataout=8'b1110_1110;

4'b1011:

dataout=8'b0011_1110;

4'b1100:

dataout=8'b1001_1100;

4'b1101:

dataout=8'b0111_1010;

4'b1110:

dataout=8'b1001_1110;

4'b1111:

dataout=8'b1000_1110;

default :

dataout=8'b0000_0010;

endcase

end

endmodule

//End of RTL code