双向8位十六进制移位寄存器_Verilog

设计要求：serinright[3:0]：右移输入十六进制数；serinleft[3:0]：左移输入十六进制数；mode[1:0]: 工作模式输入信号（“00”：清零；“01”：左移；“10”：右移）；clk: 时钟输入信号；reg7,reg6, reg5, reg4, reg3, reg2, reg1, reg0：8位十六进制显示输出信号。

解：依据题意，可给出如下的verilog代码：

module shift8(serinleft,serinright,mode,clk,reg7,reg6,reg5,reg4,reg3,reg2,reg1,reg0);

input [3:0] serinleft;

input [3:0] serinright;

input [1:0] mode;

input clk;

output [4:0] reg7,reg6,reg5,reg4,reg3,reg2,reg1,reg0;

reg [4:0] reg7,reg6,reg5,reg4,reg3,reg2,reg1,reg0;

always @(posedge clk)

case (mode)

2'b00:

begin

reg7 <= 4'h0;

reg6 <= 4'h0;

reg5 <= 4'h0;

reg4 <= 4'h0;

reg3 <= 4'h0;

reg2 <= 4'h0;reg1 <= 4'h0;

reg0 <= 4'h0;

end

2'b01:

begin

reg7 <= serinleft;

reg6 <= reg7;

reg5 <= reg6;

reg4 <= reg5;

reg3 <= reg4;

reg2 <= reg3;

reg1 <= reg2;

reg0 <= reg1;

end

2'b10:

begin

reg7 <= reg6;

reg6 <= reg5;

reg5 <= reg4;

reg4 <= reg3;

reg3 <= reg2;

reg2 <= reg1;

reg1 <= reg0;

reg0 <= serinright;

end

default:

begin

reg7 <= 4'h0;

reg6 <= 4'h0;

reg5 <= 4'h0;

reg4 <= 4'h0;

reg3 <= 4'h0;

reg2 <= 4'h0;

reg1 <= 4'h0;

reg0 <= 4'h0;

end

endcase

endmodule

为了对上述代码进行仿真，可给出如下的testbench。module tb;

reg [3:0] dataleft;

reg [3:0] dataright;

reg clk;reg [1:0] mode;

wire [3:0] reg7,reg6,reg5,reg4,reg3,reg2,reg1,reg0;

initial begin

dataleft <= 4'h0;

dataright <= 4'h0;

clk <= 1'b0;

repeat(60)

#10 begin dataleft <= dataleft + 1'b1; dataright <= dataright + 2;end

end

initial begin

mode <= 2'b00;

#200 mode <= 2'b01;

#200 mode <= 2'b10;

#200 $stop;

end

always

#5 clk <= ~clk;

shift8 x1(dataleft,dataright,mode,clk,reg7,reg6,reg5,reg4,reg3,reg2,reg1,reg0); endmodule

最后，可得到相应的仿真波形：

图1 右移仿真波形

图2 左移仿真波形