vhdl 加法器

ADD4, 8, 16

4-, 8-, 16-Bit Cascadable Full Adders with Carry-In, Carry-Out, and OverflowA

Architectures Supported

ADD4, ADD8, and ADD16 add two words and a carry-in (CI), producing a sum output and carry-out (CO) or overflow (OFL). ADD4 adds A3 – A0, B3 – B0, and CI producing the sum output S3 – S0 and CO (or OFL). ADD8 adds A7 – A0, B7 – B0, and CI, producing the sum output S7 – S0 and CO (or OFL). ADD16 adds A15 – A0, B15 – B0 and CI, producing the sum output S15 – S0 and CO (or OFL).

Unsigned Binary Versus Twos Complement

ADD4, ADD8, ADD16 can operate on either 4-, 8-, 16-bit unsigned binary numbers or 4-, 8-, 16-bit twos-complement numbers, respectively. If the inputs are interpreted as unsigned binary, the result can be interpreted as unsigned binary. If the inputs are interpreted as twos complement, the output can be interpreted as twos complement. The only functional difference between an unsigned binary operation and a twos-complement operation is how they determine when “overflow” occurs. Unsigned binary uses CO, while twos-complement uses OFL to determine when “overflow” occurs. To interpret the inputs as unsigned binary, follow the CO output. To interpret the inputs as twos complement, follow the OFL output.

Unsigned Binary Operation

For unsigned binary operation, ADD4 can represent numbers between 0 and 15, inclusive; ADD8 between 0 and 255, inclusive; ADD16 between 0 and 65535, inclusive. CO is active (High) when the sum exceeds the bounds of the adder.OFL is ignored in unsigned binary operation.

T wos-Complement Operation

For twos-complement operation, ADD4 can represent numbers between -8 and +7, inclusive; ADD8 between -128 and +127, inclusive; ADD16 between -32768 and +32767, inclusive. OFL is active (High) when the sum exceeds the bounds of the adder. CO is ignored in twos-complement operation.

ADD4, 8, 16

Spartan-II, Spartan-IIE No Spartan-3No Virtex, Virtex-E

No Virtex-II, Virtex-II Pro, Virtex-II Pro X No

XC9500, XC9500XV , XC9500XL Primitive CoolRunner XPLA3Primitive CoolRunner-II

Primitive

ADD8 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

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ADD8 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

ADD4 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

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ADD8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II Usage

This design element is schematic or inference only -- no instantiation.

VHDL Inference Code (ADD4)

architecture Behavioral of ADD is

signal sum: std_logic_vector(WIDTH-1 downto 0);

signal zeros: std_logic_vector(WIDTH-1 downto 0) := (others => '0'); begin

process (CI, A, B, sum)

begin

sum <= ('0' & A) + ('0' & B) + (zeros & CI);

S <= sum(WIDTH-1 downto 0);

CO <= sum(WIDTH);

end process;

end Behavioral;

Verilog Inference Code (ADD4)

always @ (A or B or CI)

begin

{CO,sum} <= A + B + CI;

end

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