ARM_L2C_310_Note

L2C note

important feature

1. L2C available size from 16KB to 8MB

2. 8/16-way associativity

3. fixed line length of 32 bytes/8 words/256 bits

4. interface to DATA RAM is byte writable

5. support banking on DATA RAM

6. supports all of the AXI cache modes(bit interface):

--- write-through and write-back

--- read allocate, write allocate, read and write allocate

7. Force write allocate option to always have cacheable writes allocated to L2 cache,

For processors not supporting this mode.

8. Normal memory non-cacheable shared reads --> cacheable non-allocatable.

Normal memory non-cacheable shared writes --> cacheable write-through no write-allocate.

Option: shared override. ?

9. Trustzone support.

Non-Secure(NS) tag bit used to determine securitylevel of evictions to L3.

10. Critical word first linefill

11. Pseudo-Random/round-robin victim selection policy.

12. 4X256b Line Fill Buffers(LFBs) shared by the master ports.

2X256b Line Read Buffers(LRBs) for each slave port.

3X256b Eviction Buffers(EBs)

3X256b Store Buffers(STBs)

13. outstanding access on slave/master ports

14. Prefetching capability

15. Wait, latency, clock enable, parity, error support at the RAM interfaces.

16. L2 cache event monitoring.( SPNIDEN is configured HIGH)

17. Address filtering

18. AXI master and slave interface attributes:

2x master ports

---- write issue 12 , 6 evictions/ 6 writes from STB

---- read issue 11 , 8,4 per master port, prefetches or reads from slave ports

3 reads from STB

---- combined issuing 23

---- Write ID width/Read ID width defined on slave ports

1x master port

---- write issue 12 , 6 evictions/ 6 writes from STB

---- read issue 7 , 4 prefetches or reads from slave ports

3 reads from STB

---- combined issuing 19

---- Write ID width/Read ID width defined on slave ports

2x slave & 2x master ports

---- write acceptance 6 , 3 per slave port

---- read acceptance 16 , 8 per slave port

24 , 12 per slave port for sequential accesses, when enable double linefill feature

---- combined issuing 22 / enable the double linefill feature to increase this value.

---- wirte interleave depth 2 , 1 per slave port

---- read data recorder depth 16

---- Write ID width/Read ID width defined by pl310_AXI_ID_MAX, (default is 6)

2x slave & 1x master ports

---- write acceptance 6 , 3 per slave port

---- read acceptance 12 , 6 per slave port

16 , 8 per slave port for sequential accesses, when enable double linefill feature

---- c

ombined issuing 18 / enable the double linefill feature to increase this value.

---- wirte interleave depth 2 , 1 per slave port

---- read data recorder depth 12

---- Write ID width/Read ID width defined by pl310_AXI_ID_MAX, (default is 6)

1x slave & 1x master ports

---- write acceptance 3

---- read acceptance 8

12 for sequential accesses, when enable double linefill feature

---- combined issuing 11 / enable the double linefill feature to increase this value.

---- wirte interleave depth 1

---- read data recorder depth 8

---- Write ID width/Read ID width defined by pl310_AXI_ID_MAX, (default is 6)

19. inputs are sampled on rising edges of CLK only when INCLKEN is HIGH

outputs are updated on rising edges of CLK only when OUTCLKEN is HIGH

20. AXI ID width ['pl310_AXI_ID_MAX : 0] on slave ports

['pl310_AXI_ID_MAX + 2 : 0] on slave ports

e.g. pl310_AXI_ID_MAX = 5 slave ports [5:0] and master ports [7:0]

21. AXI locked transfer

--- non-cachealbe transfer, the access is forwarded to L3 through the master ports and is marked as locked.

--- cacheable transfer, a cache lookup is always performed. when miss, a linefill, non-locked, is requested on the master side.

write accesses always cause non-locked writes on the master side.

--- when a slave performing a locked sequence, cacheable or not, the other slave is stopped from accepting more transfers.

a locked transaction is stalled until all buffers are empty, including STB.

--- processor must ensure there is only one outstanding transaction across the read and write channels during a locked sequence.

--- if multiple locked transfers come in at the same time, they are permitted to proceed in a certain priority.

priority for transfers is lockS0 > S1.

--- a locked sequence must consist of solely non-cacheable/cacheable transactions. don't mix them.

--- don't support a locked sequence starting with one locked read and one locked write at the same time one the same slave port.

22. support cacheable and non-cacheable exclusive accesses but not provide an exclusive monitor.

system need implement external exclusive monitors.

--- chacheable exclusive access, implement monitors on slave side of the cache controller.

(aware of cache controller internal status, such as the shared override bit)

--- non-cacheable exclusive access, implement monitors on master side of the cache controller.

23. cache operation: AxCACHE[3:0] ---- WA RA C B

--- non-bufferable, non-cacheable on AXI transactions [0000]

--- bufferable only AXI transactions[0001]

---cacheable bu

t do not allocate AXI transactions[0010]

--- cacheable and bufferable, do not allocate[0011]

--- cacheable write-trhough, allocate on read AXI transactions. [0110]

--- cacheable write-back, allocate on read AXI transactions. [0111]

--- cacheable write-trhough, allocate on write AXI transactions. [1010]

--- cacheable write-back, allocate on write AXI transactions. [1011]

--- cacheable write-trhough, allocate on read and write AXI transactions. [1110]

--- cacheable write-back, allocate on read and write AXI transactions. [1111]

24. AyUSERSx[0] --- shareable attribute.

Only applies to Normal Memory outer non-cacheable transactions, [0010/0011]. For other values is ignored.

Share related operation controlled by Auxiliary Control register bit[13]/[22]

25.if cache controller receive cacheable fixed transactions, AWBURST/ARBUSRTSx = 00, the results are unpredictable.

---(if cacheable, address should be increased.

for fixed transactions, it is for repeated accesses to the same location,such as when loading or emptying a periperal FIFO.)

26. Force write allocate

--- Auxiliary Control Reg [24:23]

27. Data Ram usage with banking and without banking

e.g 16ways /16KB way size

Bit[8:0] are the LSB of the RAM address bus -- without banking

Bit[6:0] are the LSB of the RAM address bus -- with banking

the [6:5] of AXI address is Bank number

28. Disable cache controller operation, the address latency is 1T in the slave ports + 1T in the master ports.

29. Stroe buffer draining policy:

--- immediately drained if targeting device memory area.

--- drained as soon as full

--- drained at each strongly ordered read/write occurrence in slave ports.

--- If the three slots of the STB contrain data, the least recently access is drained.

--- If a hazard is detected with one STB slot, it is drained to resolve the hazard.

--- drained when a locked transaction is revcived by one slave port.

--- drained when a transaction targeting the configuration registers is receiverd by one slave port.

Merging takes place only when data is in STB and it is not draining.

STB has 3 data slots, which contain a 256-bit data line. Each data slots contains a byte-valid field,

which enables the control logic to determine the data line fill level.

30. Cortext-A9 Optimizations in 310 implements.

--- Early write response (ARUSERSx[11], Auxiliary Control Register bit[30]) it disabled by default and not compatible with AXI protocol

--- Prefetch hints ( ARUSERSx[8] as 1) it is not compatible with AXI protocol.

--- Full line of zero write ( ARUSERSx[10], Auxiliary Control Register bit[0) it disabled by default and not compatible with AXI protocol

1. enable Full line of zero in 310

2. turn on 310

3. enable Full line of zero in A9

when ARUSERSx[10] as High, don't support Strongly Ordered write access

--- Speculative reads of the Cortex-A9 MPcore processor (ARUSERSx[9], only for A9, not for another ARM CPU)

--- Stroe buffer device limitation (Auxiliary Control Register bit[11]) at the same time enable this configuration bit in A9.

31. Prefetching operation

--- internal instruction and data prefetch engine

--- Double linefill issuing

--- Prefetch droppin

32. Power modes

--- Run mode

--- Dynamic clock gating

--- standby mode (connect SCUIDLE to STOPCLK input of 310)

--- dormant mode (RAM is powered up but 310 is powered down)

--- shutdown mode

33. REGFILEBASE[31:12]of L1 page talbes provides the base address for control register.

32bit only/[1:0] == 00 / burst length = 0/ non Exclusive access/ignore write strobes/write to writable register while idle

disable L2 cache when writing control register

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Errata: r3p2

Cat3

1. 729815 the "high priority for SO and Dev reads" feature can cause Quality of Service issues to cacheable read transactions

2. 754670 a continous write flow can stall a read targeting the same memory area

3. 765569 prefetcher can cross 4KB boundary if offset is programmed with value 23 (not set Prefetch Control Register(bit[4:0] as 23)